04:34
<
aeris >
adam a reçu le bidule ?
04:41
<
lekernel >
ah, je ne sais pas, je demande
04:41
<
lekernel >
tu vas au fosdem au fait?
04:47
<
roh >
hackabledevices down?
05:00
<
wolfspraul >
lekernel: nice, congrats for the article!
05:01
<
wolfspraul >
ha, Anika Kehrer again - she's cool!
05:58
<
roh >
hm. found a bug. it was 27c3 not 26c3 ;)
05:59
<
lekernel >
no, i did present it at 26c3
06:00
<
kristianpaul >
and booted linux at that time ;-)
06:00
<
rejon >
lekernel where you staying at for fosdem?
06:01
<
lekernel >
at a hotel
06:02
<
rejon >
looking for pointers
06:02
<
rejon >
b4 i get ripped off
06:07
<
roh >
lekernel: ah.. ok. so you have 2 congresses on it now ;)
06:08
<
roh >
good things need time
06:08
<
lekernel >
well, only 26c3 was successful. they really fucked up the workshops at 27
06:13
<
lekernel >
rejon: hotel bloom, rue royale
06:21
<
wolfspraul >
lekernel: btw Adam is working on the power-up bug
06:21
<
wolfspraul >
he went to xilinx last week and spent 2.5h there, discussing the thing. he has some new ideas he is trying now (just in case you don't already know all this)
06:22
<
lekernel >
he found it, didn't he?
06:23
<
lekernel >
from my understanding, it's a race condition between fpga and flash startup, and for some reason (Adam didn't tell me why) the capacitor I had planned to solve this potential problem didn't work as expected
06:27
<
rejon >
lekernel cool
06:28
<
wolfspraul >
lekernel: I don't know, I am waiting.
06:29
<
wolfspraul >
I hate to cause stress on people.
06:29
<
wolfspraul >
let him do his proper work until he is happy :-)
06:29
<
wolfspraul >
if he found it - great!
16:02
<
kristianpaul >
hola
17:00
<
mumptai >
the fpga is the only device on the jtag chain on the mm1?
17:00
<
mwalle >
mumptai: yes
17:01
<
mumptai >
okay, then i got to read more, thx
17:10
<
mumptai >
did the urjtag systax hange lately?
17:11
<
mumptai >
i'm getting a syntax error with that fjmem batch
17:11
<
mwalle >
i dont think so
17:11
<
mwalle >
what error
17:11
<
mumptai >
this one: "Error: part.c:355 urj_part_instruction_define() invalid parameter: invalid instruction length"
17:13
<
mumptai >
which is the response to: "instruction CFG_OUTÂ Â 000100 BYPASS"
17:13
<
mwalle >
did the detect return successfully?
17:14
<
mumptai >
it detects the prom an the spartan
17:14
<
mwalle >
what board
17:14
<
mumptai >
and i select the later one with "part 1"
17:20
<
mwalle >
unfortunately, i dont have a working urjtag right now, but i tried it with my spartan 3e eval board
17:20
<
mwalle >
are you sure you've chosen the right part?
17:21
<
mwalle >
there is a command which should display the instruction length
17:22
<
mumptai >
detect does
17:22
<
mumptai >
IR length is 14
17:26
<
mwalle >
the complete chain?
17:30
<
mumptai >
it says "non" multiple times
17:30
<
mumptai >
s/non/none/
17:31
<
mwalle >
could you paste it somewhre
17:31
<
kristianpaul >
mumptai: did you : instruction CFG_OUTÂ Â 000100 BYPASS
17:31
<
kristianpaul >
instruction CFG_INÂ Â 000101 BYPASS
17:31
<
kristianpaul >
before pld load right?
17:31
<
mumptai >
there is one row
17:31
<
mumptai >
labled as No. 1
17:32
<
mumptai >
no mfg., no part
17:32
<
mumptai >
and Stepping instr. and register are "(none)"
17:33
<
mumptai >
kristianpaul, yes
17:33
<
mwalle >
and detect detect, detects a xilinx device?
17:34
<
mumptai >
and says that is can't find info about the stepping
17:34
<
kristianpaul >
paste i tsomwhere
17:34
<
mumptai >
but it decodes the IDs correctly
17:35
<
mwalle >
ah ok, so you have to add the stepping in data/xilinx/<part>/STEPPINGS
17:35
<
mwalle >
did it ever work?
17:36
<
mumptai >
but that wasn't in the interactive mode
17:38
<
mwalle >
with exactly that fpga?
17:38
<
kristianpaul >
mumptai: what jtag cable are you using btw?
17:41
<
mwalle >
i guess you are using the onboard 'cable' of the nexys2?
17:41
<
mumptai >
works better with proper scan files ;)
17:42
<
mwalle >
but why have it worked before?
17:42
<
kristianpaul >
mumptai: [OT] are you aware if there is support for Bus pirate from urjtag project?
17:43
<
mumptai >
kristianpaul, no wasn't. but i can actually load a bit-file into the fpga using urjtag, so it can't be that broken ;)
17:44
<
mwalle >
kristianpaul: have you tried the bus pirate with urjtag?
17:44
<
mwalle >
last time i tried it was very slow
17:45
<
kristianpaul >
mwalle: but, but i willing to do so with my avnet board
17:45
<
kristianpaul >
s/but/no
17:46
<
kristianpaul >
try  frequency 12000000 ??
17:48
<
mumptai >
the tck rate is actually hard-coded into the cable's controller code
17:50
<
mumptai >
its a cypress fx2 running some altera usb-blaster emulation
17:52
<
mumptai >
maybe i messed up the ucf, or the flash isn't yet supported
17:53
<
mumptai >
will double check that when i find another spare evening
17:54
<
mwalle >
mumptai: i guess your are too fast for the flash detection
17:54
<
mwalle >
you get the same error with the FT2232H if you dont set the frequency to 6MHz
17:55
<
mumptai >
its not really running at 12MHz, probably not even above 2MHz
17:55
<
kristianpaul >
did flash memory mind about it? it seems..
17:55
<
mumptai >
that is a 8051 core doing some bit-banging ...
17:56
<
kristianpaul >
is not that worst? :) (bit bang?.. above 2Mhz..)
17:56
<
kristianpaul >
mumptai: can you confirm with flash memory data sheet?
17:57
<
mumptai >
i can, but i got to get up in less than 7 hours
17:59
<
mumptai >
so, good night
17:59
<
mumptai >
and thanks for you help
18:00
<
kristianpaul >
sure
18:00
<
kristianpaul >
hey 7 hrs still un fair !
18:01
<
kristianpaul >
sleep from 5 to 6 hrs a day is posible :-)
18:01
<
mwalle >
im going to bed too