<kristianpaul>
interesting bet from altera to mips, compared to xilinx with arm ;)
<kristianpaul>
and with a softprocesor not cpu in the chip
<kristianpaul>
so nios is died..
<kristianpaul>
s/died/dead
<azonenberg>
kristianpaul: What about MIPS on xilinx?
<azonenberg>
is building a mips softcore
<wpwrak>
lekernel: (compressor_two.v) interesting ... no if ... <block> ... ? :)
<lekernel>
wpwrak: no and no documentation or test bench either
<wolfspraul>
and no reply in irc, so far :-)
<lekernel>
got one yesterday
<lekernel>
so: he claims it works
<lekernel>
and wouldn't contest this code dump is a stinking mess
<wpwrak>
lekernel: who needs documentation or testing if it works ? ;-))
<lekernel>
well he did write a test bench
<lekernel>
you can't pull off a complex piece of code like this without simulation
<lekernel>
but
<lekernel>
he did that incrementally, overwriting the test bench without keeping any history
<wpwrak>
burn, bridges, burn ! ;-)
<lekernel>
so now there's _one_ test bench in the repository, and it's even messier than the rest of the code
<lekernel>
also, he also integrated quite tightly the sdram controller with the rest of the code, which means there is sdram-specific stuff all over the place
<wpwrak>
reminds me of those "real programmers" jokes :)
<lekernel>
it's horrible, really
<lekernel>
and in fact I'm impressed he managed to get anything to work with such methods
<wolfspraul>
not surprised to hear this
<wolfspraul>
he's a physicist, and then self-taught software engineer, electrical engineer, mechanical engineer, layout engineer, ic designer, ...
<wolfspraul>
and the worst is that afaik there never has been any serious amount of outside contribution to any of his stuff
<wolfspraul>
so the bottom line is that the code is not reusable?
<lekernel>
no, it's not
<wpwrak>
lekernel: is anything in there that can be useful for a new implementation, or not even that ?
<lekernel>
I don't think so... maybe the architecture if it were documented :-P
<lekernel>
there's one block diagram in a xcell article, but that's about how far as it goes
<wpwrak>
okay, saves about 5 minutes :)
<lekernel>
even the indentation/style (or lack thereof) is awful
<lekernel>
and there are tons of code commented out all over, you're always wondering why
<wpwrak>
(indentation style) yeah, never fails as a warning sign
<wpwrak>
(commented-out code) reminds me of my vga experiments ;-)
<kristianpaul>
azonenberg: mips altera sorry
<juliam_c>
Hello, first sorry for the length of my msg; i programed the Milkymist SoC on my Terasic DE1 Board which has a SDR-SDRAM. I adapted the wb_sdr_ctrl provided by lattice semi and it seems to work fine, i compiled and stored on flash the milkymist bios (using lm32-elf- toolchain downloaded from lattice web) and mr, mw commands shows that writing and reading to SDRAM is OK. I'm now trying to run uclinux with serialboot and flterm, i downloaded from your git
<juliam_c>
1. When i compiled with make vmlinux i get an error with the early_printk.c which i solved by excluding this function with menuconfig. the error occurs With both lm32-elf- and lm32-linux-
<juliam_c>
2. When i try to serialboot (with flterm) the image is copied to RAM from 0 to 100% and then it stops with a line that says "DONE" and thats all. I reset the board and noticed that the image vmlinux.bin is stored from 0x40000000 to 0x400(the size of the binary) and every seems to be right... i say "seems" becouse i compare the contents of the binary file with the readings using milkymist bios and the first lines and last lines are the same...
<juliam_c>
*are the same with the file's lines
<juliam_c>
Please could anyone give me some advices, what should i do...
<lekernel>
juliam_c: as far as I know, the lattice sdram controller license is not compatible with the GPL that MM SoC uses
<juliam_c>
But isnt it the same license of the lm32_top??? for me it has been an issue too, where can i find more about that
<juliam_c>
I though all those components where the same as lm32...
<juliam_c>
I designed a controller for my board's ram but it's AMBA AHB interfaced maybe i could do the required modifications to make it wishbone compatible... but in conclusion do you mean can not use the lattice's design with MM SoC on my altera FPGA?????