<azonenberg>
The interconnect muxes are now decoded for function block 1
<azonenberg>
only four unknown fields left in the macrocell config
<azonenberg>
and three or four global muxes to work out
mumptai has quit [Ping timeout: 248 seconds]
<wpwrak>
time to draw the rest of the map :)
<wpwrak>
btw, if you mean this graphical format to be useful for more than a quick visual impression, then it may help if you'd add horizontal and vertical lines to the arrays
<azonenberg>
wpwrak: This is a debug visualization
<azonenberg>
i plan to do something more substantial down the road for reverse engineering
<azonenberg>
But users of the toolchain will not have any real use for this
<wpwrak>
good then :)
<azonenberg>
Basically i'm writing RTL that is explicitly constrained to the maximum extent possible (so that very little is left up to the compiler)
<azonenberg>
synthesize it, then verify that my output matches
<azonenberg>
As you can see there are still a half-dozen fields or so that aren't decoded
<wpwrak>
and only part of the routing is shown
<azonenberg>
The sample design only uses function block 1
<azonenberg>
FB2 is legitimately blank
<azonenberg>
That said, my code has not yet figured out all of the muxes for FB2
<azonenberg>
the unknowns are, first, which settings to use for FFs and IBUFs in FB2 to rout to FB1
<azonenberg>
and second, whether FB2 uses the same mux settings or different ones
<azonenberg>
All of the mux work will have to be redone for each device in the family since the mux is different widths, but i've mostly automated it
<azonenberg>
so it shouldn't be too bad
<wpwrak>
macrocells are hardwired to pins ? or can they choose among pins ?
<azonenberg>
A macrocell is hard-wired to one pin
<azonenberg>
But, not exactly
<wpwrak>
yeah, cracking the first one is generally the hardest bit. then it gets boringly easy :)
<azonenberg>
Each output buffer can be driven either by its attached macrocell's combinational logic, or that macrocell's flipflop
<azonenberg>
The input buffers drive global routing as well as a high-speed path to the D input of the associated macrocell's flipflop
<azonenberg>
the alternative input for the FF is the combinational path of the same macrocell
<azonenberg>
When the IBUF drives the flipflop, the combinational logic is available for internal use or driving non-registered outputs
<azonenberg>
i still have a decent amount of work to do to write a synthesis, mapping, and PAR toolchain for the architecture
<azonenberg>
Step 1 is figuring out what config bits to set to put each mux in the datasheet block diagram in a desired state
<wpwrak>
looks nice so far :)
<azonenberg>
Step 2 is taking a mapped netlist (as in, structured in the form of sum-of-product expressions with no more than X inputs at each level, D/T flipflops and latches, and I/O buffers) and packing it into the device
<azonenberg>
including finding places where i can use a function-block level control term rather than a separate product term for (say) each flipflop's clock enable
<azonenberg>
Step 3 is taking a generic gate-level RTL netlist and mapping it into the CPLD-friendly form
<azonenberg>
Step 4 is figuring out how to use iverilog, ghdl, or a homebrewed synthesis tool to turn HDL into generic gate-level RTL
<azonenberg>
and obviously all the way down the stack i need to be able to attach constraints to the netlist like "put this flipflop in this macrocell" or "this signal goes on that pin"
<azonenberg>
So right now i'm still on step 1
<azonenberg>
At some point I also have to decide on how to release this
<wpwrak>
yeah, manual overrides can be very useful. also when you have some things that aren't implemented yet. then you just "override" everything.
<azonenberg>
Yeah
<azonenberg>
Or if you want to try out-optimizing my optimizer
<azonenberg>
Which probably won't be hard
<azonenberg>
Anyway right now i have one master repo for everything i've been doing lately which includes my thesis research, libjtaghal, and libcrowbar (the CPLD stuff)
<wpwrak>
(release) you mean, politely ask for the front page of time magazine ? :)
<azonenberg>
I'm not ready to release the thesis stuff yet
<azonenberg>
both libjtaghal and libcrowbar need lots of cleanup and documentation
<azonenberg>
So i have to decide whether to split the repo into multiple ones, release a tarball but not have public version control\ access, etc
<azonenberg>
Or whether to keep on working in my current semi-public mode until i finish my thesis
<azonenberg>
and just dump the whole thing on sourceforge/github/whatever
<azonenberg>
There's zero doubt whatsoever that (at the latest) when i finish my thesis the entire repo will be relased somewhere under 3-clause BSD
<azonenberg>
What's still uncertain is whether there will be intermediate releases of the support libraries in the short term
<wpwrak>
why the need for secrecy ? seems rather unlikely that someone would plagiarize work you published in a way that hurts you
<azonenberg>
You mean my thesis stuff or what?
<wpwrak>
yes, the things that go into it
<azonenberg>
I don't want to dump code out somewhere until i have a paper that talks about the science behind it
<wpwrak>
if there's one "wow" moment, maybe you want to keep that to yourself, for effect. but all the rest ...
<azonenberg>
I have a survey paper that sets the stage for what i'm doing
<wpwrak>
don't you publish papers as you go ?
<azonenberg>
once that is submitted i'll re-evaluate what to publish immediately and what to hold back on
<azonenberg>
I'm almost ready to submit the first one
<azonenberg>
only been working on this for a year and a half and the first year was mostly coursework
<wpwrak>
thesis advisor not yet breathing down your neck ? :)
<azonenberg>
Lol he's decently happy with what i've been doing so far
<wpwrak>
heh. what has "publish or perish" come to ? ;-)
<azonenberg>
Lol, well i have 15 pages i sent to him and the other guys in the research group for a review
<azonenberg>
waiting for suggestions
<wpwrak>
that's already two papers. conference tend to like things short.
<azonenberg>
It's a survey paper so it'd go in a journal
<wpwrak>
okay, that'll work then
<azonenberg>
And will also turn into the related-work section of my thesis
<azonenberg>
so if i have to strip it down a bit for publication that's fine
<wpwrak>
of course. writing the actual thesis is mainly copy & paste :)
<azonenberg>
I suspect that 44 references is a little bit long for a conference paper
<wpwrak>
3 per page. not too bad. but of course the overall length would be frowned upon.
<azonenberg>
Yeah, like i said i'm not even considering submitting it to a conference
<azonenberg>
perhaps original research in six months or so
<azonenberg>
but journals are a more proper venue for survey papers anyway
<azonenberg>
The survey paper outlines the problem i'll be doing my thesis on so once i get that out i'll probably move my repo to full-on public
<azonenberg>
right now i have a viewer on a Redmine install that doesn't require a password but isn't linked anywhere
<wpwrak>
sounds good
<azonenberg>
as in, i'm not exactly trying to hide but i don't think i have enough to show yet to go out of my way to publicize it
<azonenberg>
Most of the code i have now is libjtaghal, libcrowbar, an old MIPS softcore that is going to get replaced by a new design soon, and the NoC i'll be building all of the fun stuff on
<wpwrak>
you can also have some less academic papers on technical details
<azonenberg>
I intend to do a few tech reports etc
<wpwrak>
ironically, these may end up getting a lot more citation than the rest :)
<azonenberg>
or maybe just jam something up on my website
<azonenberg>
Lol
<azonenberg>
I'm not out to get a million citations or sell my work to some company and get rich or whatever
<azonenberg>
i just want to get a phd, hopefully make a useful contribution to the field, and then go find a lab that likes what i've been spending the last few years on enough to hire me :p
<wpwrak>
e.g., for linux-related stuff, i had papers at linux-kongress, linux symposium, etc. these are not academic events, but you still get the word out
<azonenberg>
Yeah
<azonenberg>
Well I have my hands in so many places with this work its not even funny
<azonenberg>
i'm doing SoC architecture, NoC, CPU microarchitecture, security, networks, OS architecture
<azonenberg>
i'm citing stuff ranging from IEEE papers to ACM journals to Vanity Fair to declassified NSA memos
<wpwrak>
sounds as if focus may become a topic soon :)
<azonenberg>
Not really
<azonenberg>
There is a central theme to it all
<azonenberg>
but it's interdisciplinary
<wpwrak>
but then, it's not so bad to err on the broad side at the beginning
<azonenberg>
and thus related work is everywhere depending on which end i'm grabbing from
<azonenberg>
I mean, when you look at stuff like fault attacks on crypto (similar but not what i'm doing)
<azonenberg>
you need to know the math and the hardware since either by itself isn't exploitable
<azonenberg>
but the combination is vulnerable
<wpwrak>
sure. that's 2-3 fields. you had a lot more. there's likely to be a point beyond which you need things only for illustration but not as part of the core research
<wpwrak>
where illustration can mean a proof of concept
<azonenberg>
Well, my focus is on securing applications
<azonenberg>
by using an OS architecture including some hardware components inside a SOC
<azonenberg>
Connected by a NoC
<azonenberg>
and using a CPU with a few ISA tweaks to optimize performance for the platform
<azonenberg>
So...
<wpwrak>
sounds like at least two theses (sp?) folded into one :)
<wpwrak>
since you'll of course also need to tweak a compiler then ...
<azonenberg>
Nope
<azonenberg>
Thats the beauty of it
<azonenberg>
it's microarchitecture tweaks, plus repurposing the "syscall" instruction while keeping the same machine syntax
<wpwrak>
so the compiler won't see the new instructions ?
<azonenberg>
that's not an instruction the compiler generates anyway
<wpwrak>
ah, okay
<wpwrak>
so no new compiler needed for now. maybe later :)
<azonenberg>
Most of the interesting stuff in the CPU is related to register file and pipeline tweaks for efficient multithreading
<azonenberg>
but that's all RTL modifications
<azonenberg>
i'm taking great pains to make sure it'll work with gcc
<azonenberg>
Unmodified gcc
<wpwrak>
;-)
<azonenberg>
Which means emulating things like branch delay slots even if the microarchitecture doesn't strictly require them
<azonenberg>
I'll probably cut a few of my planned ideas and simplify stuff
<azonenberg>
But i might keep working on it in my spare time after i graduate
<azonenberg>
because this is what i plan on using to run my homebrew laptop
<azonenberg>
Anyway, enough talking about code i haven't yet written :p
<azonenberg>
things are likely to change a lot before i actually get to that point
<wpwrak>
there is precedent for such things happening :)