11:07 <GitHub121> [mibuild] sbourdeauducq pushed 1 new commit to master: http://git.io/y76JJw

11:07 <GitHub121> mibuild/master d60ab1d Sebastien Bourdeauducq: Use new 'specials' API

11:54 <GitHub17> [milkymist-ng] sbourdeauducq pushed 2 new commits to master: http://git.io/eatXsA

11:54 <GitHub17> milkymist-ng/master 0caac22 Sebastien Bourdeauducq: Use new 'specials' API

11:54 <GitHub17> milkymist-ng/master a22ada3 Sebastien Bourdeauducq: corelogic -> genlib

11:54 <GitHub139> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/sGsrNQ

11:54 <GitHub139> migen/master 55ab01f Sebastien Bourdeauducq: fhdl/specials/Instance: _printintbool -> verilog_printexpr

14:47 <GitHub183> [mibuild] sbourdeauducq pushed 1 new commit to master: http://git.io/8fME-g

14:47 <GitHub183> mibuild/master 2b902fd Sebastien Bourdeauducq: xilinx_ise: import Instance

14:53 <lekernel> Fallenou, seems the CFG2 CSR is missing from your binutils

15:08 <GitHub0> [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/GOgN-A

15:08 <GitHub0> milkymist-ng/master 43343b1 Sebastien Bourdeauducq: lm32: use submodule

15:28 <larsc> ha, found another way to store away the clobbered registers without clobbering the userspace stack. Load the address of the memory where we are going to store them into r0, and reset r0 to 0 after the registers are saved.

15:30 <lekernel> yeah, the debugger rom does that

15:39 <GitHub155> [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/Mj3i8Q

15:39 <GitHub155> milkymist-ng/master b854f1a Sebastien Bourdeauducq: build: support optional MMU

15:39 <Fallenou> lekernel : oh, I will have a look at that, thanks

15:48 <mwalle> hi

15:49 <lekernel> hi

16:01 <GitHub187> [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/ifolPw

16:01 <GitHub187> milkymist-ng/master 5e6505b Sebastien Bourdeauducq: bios: print number of memory errors

16:10 <lekernel> interesting. switching DDR clock I/O standard from SSTL2_I to SSTL2_II has reduced the number of errors from 50k-80k to 100-200

16:10 <lekernel> on a 4MB buffer

16:14 <GitHub108> [lm32] mwalle pushed 1 new commit to master: http://git.io/Arq4WA

16:14 <GitHub108> lm32/master cf2281b Michael Walle: fix compilation with no CFG_DEBUG_ENABLED...

16:22 <mwalle> lekernel: isnt dd if=infile of=outfile conv=swab the same as your "byteswap" tool?

16:23 <lekernel> hmm, should be :)

16:24 <mwalle> "software: go back to GCC" << huh?

16:33 <lekernel> grmbl. swapping PLL outputs that are otherwise configured exactly the same makes the SDRAM bug appear and disappear.

16:33 <lekernel> I hate xilinx

16:47 <wpwrak> meanwhile, at xilinx HQ, champagne is flowing. CEO announces that the company's secret long-term objective has been met: they have officially earned sebastien's hatred. stock soars.

16:53 <GitHub5> [milkymist-ng] sbourdeauducq pushed 2 new commits to master: http://git.io/7ya44g

16:53 <GitHub5> milkymist-ng/master 356416f Sebastien Bourdeauducq: lm32: update

16:53 <GitHub5> milkymist-ng/master 70f4c74 Sebastien Bourdeauducq: m1crg: advance off-chip DDR clock phase

16:53 <lekernel> now I wonder if it's sill going to work on r1 boards...

16:54 <lekernel> either way, my board's dram is ready to receive sampled hdmi frames ;)

17:00 <lekernel> mwalle, byteswap != dd conv=swab. byteswap also reverses the bits in the 16-bit words.

17:01 <lekernel> AFAIR this is a xilinx configuration oddity, not a minor M1 PCB mess-up...

21:36 <larsc> wpwrak: if that's their secrect plan it may explain a few things ;)

21:57 <wpwrak> ;-))

21:57 <wpwrak> all the design decisions suddenly make sense :)

23:18 <GitHub25> [lm32-binutils-mmu] fallen pushed 1 new commit to master: http://git.io/JSwpCQ

23:18 <GitHub25> lm32-binutils-mmu/master cd0bade Yann Sionneau: lm32: Add support for CFG2 CSR register

23:22 <Fallenou> if you re-arrange the short SHA-1 you get: c0de bad :-(

23:22 <Fallenou> too bad!

23:22 <Fallenou> gn8!