lekernel changed the topic of #milkymist to: Milkymist One, Migen, Milkymist SoC & Flickernoise :: Logs: http://en.qi-hardware.com/mmlogs
<wpwrak> hackers committing their stuff before going for a saturday evening beer ?
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<GitHub177> [milkymist-ng] sbourdeauducq pushed 7 new commits to master: http://git.io/Zt4j9A
<GitHub177> milkymist-ng/master fb9a278 Sebastien Bourdeauducq: dvisampler/charsync: fix found_control signal
<GitHub177> milkymist-ng/master e06585d Sebastien Bourdeauducq: dvisampler: clean up EDID data
<GitHub177> milkymist-ng/master 80f3e97 Sebastien Bourdeauducq: software/stddef.h: c++ compat for NULL
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<kristianpaul> lekernel: any -ng news worth to mention to the ML?
<kristianpaul> has been a while since i heard too much about i think..
<lekernel> well it's getting DVI input https://github.com/milkymist/milkymist-ng/commits/master
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<wpwrak> signal integrity solved ?
<lekernel> not yet... this sort of things makes me feel like throwing my computer out of the window and reducing my m1 to pieces with a baseball bat, so I try to postpone them
<lekernel> and I've been trying to get the data interface to work, which is a complete disaster and the xilinx crapware keeps breaking, so I'm really not in the mood for such frustrating and slow activities
<lekernel> PLL loses lock, weird and random bit errors appear, etc.
<lekernel> that is, when i can test things at all, sometimes some apparently harmless modification makes the heuristic p&r pick the bad routes and the system doesn't boot at all
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<wpwrak> hmm, i remember such violent emotions from last weekend, when one disk after another failed ...
<wpwrak> (p&r) you mean it misses the timing constraints ? or does p&r just produce an invalid configuration ?
<wpwrak> (pll) do you feed an input into a PLL ? if yes, signal integrity issues could very well explain loss of lock
<lekernel> most of the times when it doesn't work, it does miss the timing constraints... and usually in a completely unrelated part of the design
<lekernel> yes, I'm sending the HDMI clock signal, which goes through a 8ns!!!!! route around the slowtan6 chip before reaching the PLL
<wpwrak> lovely :) can you lower the resolution, to require a lower speed ? that way, you'll only have to fight that problem when the rest works
<lekernel> I don't see the PLL losing lock at 640x480 60Hz though
<wpwrak> at what clock do you run ?
<lekernel> that's a 25.175MHz pixel clock
<lekernel> data on each HDMI line go at 10 times that, 251.75Mbps
<lekernel> and I also need a 20x clock for oversampling and running the phase detector
<lekernel> which supposedly puts the sampling in the middle of the data eyes
<lekernel> ...using another crippled s6 feature, the iodelay, with >300% PVT, etc.
<lekernel> since everything I have put after the phase detector/data sampler works intermittently or doesn't work, next step I'm going to send the raw data into the DRAM and try to see if much of it is correct, or if I'm sampling mostly garbage
<lekernel> btw xilinx has removed the shitty iodelay from the 7 series and replaced it with something more serious...
<wpwrak> yeah, that sounds like a reasonable approach. unfortunately, you get quite high speeds, even at a moderate resolution
* lekernel wonders if autogenerating http://pastebin.com/akEvPKjM is a good idea
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<wpwrak> why ? if you really need it ...
<Fallenou> 00:20 < sh4rm4> also, is there some kind of official mmu (sold as lattice IP) ? < as far as I know there isn't any
<Fallenou> 00:19 < sh4rm4> Fallenou, saw your binutils commit - does that mean the MMU is 100% finished now ? < 100% finished I think almost yes, 100% debugged I'm sure not :)
<Fallenou> sh4rm4: milkymist-ng soc can boot with the mmu synthetized inside the lm32 softcore cpu. which means it does not break the cpu :)
<Fallenou> but for now there is no software making any use of any MMU feature
<Fallenou> there are unit tests which are running successfully on a simulated lm32-mmu
<Fallenou> so it seems to be near OK, at least :)
<Fallenou> I hope that in a few weeks/months I will have a NetBSD kernel which will use the lm32 MMU
<Fallenou> and then I will be able to debug the last pieces
<Fallenou> I'm pretty sure it can't work fine the first time :p obviously.
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<sh4rm4> Fallenou, but the design of the mmu is complete ?
<Fallenou> yes
<Fallenou> it has the minimal feature set necessary for running an OS using virtual memory
<Fallenou> itlb / dtlb
<Fallenou> read write right management
<Fallenou> it generates exceptions upon tlb miss and page faults
<Fallenou> (no hardware page tree walker)
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<sh4rm4> cool
<Fallenou> yes that's pretty cool :)
<Fallenou> I hope someday we will have a nice NetBSD booting on Milkymist (and Milkymist-ng) SoCs on the M1
<sh4rm4> i hope someday we'll have a full linux + musl libc port for lm32
<Fallenou> hehe, it's up to you :)
<Fallenou> or somebody else
<Fallenou> gn8 !
<Fallenou> see you
<sh4rm4> bye
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<GitHub25> [milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/4FMfsg
<GitHub25> milkymist-ng/master 3640cab Sebastien Bourdeauducq: software/common.mak: add C++ definitions
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