<lekernel>
I cut open a cheap HDMI cable with the intention of shortening one data pair to check that my design would detect and compensate for the added skew
<lekernel>
there are no pairs lol, just conductors in bulk
<lekernel>
this shines an interesting light on the earlier DDC problems. high impedance (5k) signals buried among 8 signals switching at hundreds of MHz for 3 meters doesn't sound quite right.
<lekernel>
I wonder if my monitor is capable of dealing with such a cable...
<lekernel>
if so maybe adding some hundred-ish pF capacitor on the DDC signals at the HDMI adapter card would help filtering some of the crosstalk
<lekernel>
aha! I found a I2C EEPROM datasheet that recommends adding such a capacitor (plus a series resistor, even) on SCL for DDC applications
<larsc>
or you do the filter in hdl
<lekernel>
well that windowing + average somehow didn't work... and I won't bother further if a 0.1 cent capacitor solves the problem
<lekernel>
how are you, by the way?
<larsc>
good
<larsc>
leaving the hospital tomorrow
<larsc>
and the food here isn't even that bad
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<Fallenou>
good to know you're ok !
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<GitHub8>
[milkymist-ng] sbourdeauducq pushed 3 new commits to master: http://git.io/bSGZLQ
<GitHub8>
milkymist-ng/master a6a3d93 Sebastien Bourdeauducq: software: add videomixer base files
<lekernel>
hmm, with TMDS if the last bits received are a control word (eg 1101010100) do I always know I'm at a word boundary? or can I ever get 1101010100 from the concatenation of parts of two other valid symbols?
<larsc>
aren't there sync symbols?
<larsc>
I think the idea is that you can't get one of the sync characters by accident
<larsc>
so it should work
<lekernel>
The high-transition content of the characters transmitted during the blanking period form the basis for character boundary synchronization at the decoder. While these characters are not individually unique in the serial data stream, they are sufficiently alike that the decoder may uniquely detect the presence of a succession of them during transmitted blanking intervals. The exact algorithm for this detection is an implementation detail
<lekernel>
beyond the scope of this document, but minimum conditions for receiver synchronization are defined.
<lekernel>
why make it simple ....
<lekernel>
and then it just says "3.3.2 Data Synchronization The receiver is required to establish synchronization with the data streams during any blanking period greater than 128 characters in length."
<lekernel>
omg the xilinx application note code is again full of "rawdata <=#1 rawword;" and "synthesis parallel_case full_case"
<larsc>
it's probably in their coding style guidlines that this is a good idea, wouldn't surprise me
<_florent_>
why not dumping a complete data stream to the ddr and send it to your computer over serial or udp and try to undersand every thing and reconstruct the frame using python for example?
<_florent_>
and use it in your simulation for prototyping
<larsc>
that's half the fun
<larsc>
(but twice as productive) ;)
<lekernel>
only if I run into bugs
<_florent_>
don't know if if can be useful, but I'm working on the refactoring of miscope
<_florent_>
should be working in a few days
<_florent_>
it can output vcd files
<_florent_>
and use migen if course
<lekernel>
I wonder how hard it would be to use Wolfgang's fpgatools to dynamically reroute signals to the analyzer in no time
<lekernel>
similar to what Werner did with xdl, minus the proprietary bloatware
<lekernel>
if there are no glitches, you could even reroute while the fpga is running, using partial reconfiguration
<lekernel>
yeh but their character synchronizer is a nonportability-optimized hard block
<antgreen>
does xilinx ship any tool to help visualize they mapping of your design?
<lekernel>
mapping at what level?
<antgreen>
I mean, I want to see how the FPGA is being used at the physical level
<lekernel>
yes, with fpga editor
<antgreen>
bah.. that garbage won't run on my Fedora box
<antgreen>
missing the right motif libs
<lekernel>
if you don't care about the placement, just what type of resources are being used and how they are connected, you can open the netlist with the less buggy planahead
<antgreen>
I just want a fun picture
<lekernel>
planahead can show you some of the placement too
<lekernel>
but not the detailed routing
<larsc>
antgreen: I just linked the version of the lib it wants to and newer version, works fine
<lekernel>
it could be enough for a fun picture
<antgreen>
will try
<antgreen>
which file do I open with planahead?
<lekernel>
ncd I guess
<lekernel>
but you need to go all the way through, create a "new project" etc.
<lekernel>
fpga editor doesn't have this bureaucracy, but the UI is still pretty horrid
<antgreen>
symlink created. now it's asking for an older libstdc++. hopefully there's a compat package
<lekernel>
yeh there is
<antgreen>
you'd think motif would be gone by now
<lekernel>
and then you need to do export DISPLAY=:0
<lekernel>
and make sure the old x11 bitmap fonts are installed