<_florent_>
in fact I want advantage of both : declaring as solution 1 and using it with individual signal or bus ;)
<lekernel>
ah sorry, I misunderstood your question
<_florent_>
no pb
<lekernel>
no, there is nothing implemented for obtaining part of a resource
<_florent_>
hmm ok, do you want that I try to implement it?
<lekernel>
I like the simplicity of the current solution, but if you feel there's a real need for that, you can try proposing something else...
<lekernel>
you could also just have some "resource builder" functions... that return solution 1
<_florent_>
I can try that
<_florent_>
that's just that I do want to change the platform file according design I'm implementing
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<lekernel>
anyone has done tests on the hard IOB and routing switching limits?
<lekernel>
connect output pin to input pin, and increase frequency until the fpga can't keep up
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<lekernel>
considering that the PLLs have a VCO with 8 phases that goes over 1 GHz, if you can manage skew, jitter and IOB/routing switching you should be able to sample IO over the 950MHz offered by ISERDES
<_florent_>
the implementation of what I was asking in the afternoon:
<lekernel>
this code is modifying the platform description
<lekernel>
_ressource_regroup(self.description, r) then description.remove(ressource)
<lekernel>
request() should only register requests, not do any actual matching
<lekernel>
and then, even _match doesn't modify the platform description
<_florent_>
yes that's maybe not very clean, you see a better place to do it?
<lekernel>
to be honest I don't see a need for that, you can simply call request() in a loop when you need to do this sort of thing (which probably isn't often, I think)
<_florent_>
iirc it was not working with a loop
<lekernel>
for i in range(8): plat.request("led", i, leds[i]) - you may need to make it accept signal slices
<_florent_>
slice object was not working iirc
<lekernel>
for i in range(8): self.comb += plat.request("led", i).eq(leds[i]) would definitely work
<_florent_>
ok thanks
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<_florent_>
for the moment I will use my solution, but if I realize I don't really need it I will switch to yours
<lekernel>
why use last_state instead of next_state?
<lekernel>
and you don't need a dict, you can iterate on self.when_entering_actions directly
<_florent_>
for last_state vs next_state, I'm executing the actions only when I am in the state and when I'm out of the state, but it's maybe better with next_state
<_florent_>
since when_entering is executed in my code when I'm already in
<lekernel>
yes, there is a one clock cycle difference
<lekernel>
and with last_state it results in shorter combinatorial paths which is always good eg when using slowtan 6
<lekernel>
but it takes one more register
<lekernel>
both solutions are ok, I just want to make sure we understand the difference
<_florent_>
my need for when_entering is generally to trigger an action on the first clock cycle of a state
<lekernel>
so 1) remove the when_entering_cases/when_leaving_cases dicts and iterate on the lists directly 2) remove the old entering()/leaving() functions
<lekernel>
and it's ok
<lekernel>
alternatively, make everything dicts in the first place (you can use defaultdict(list))
<_florent_>
just that I'd like to keep the entering & leaving since It can be useful for others needs...
<lekernel>
but you'll need to order by key when adding to the comb list, otherwise there will be non-determinism problems
<lekernel>
no, all code that doesn't have an actual use case should be removed
<_florent_>
I'm using it ;) ( I found it useful, just want to keep it in my fork, but I understand if you don't want it)
<lekernel>
how about you just reference _state etc. directly?
<lekernel>
and why not replace with when_* functions?
<_florent_>
and use it like:
<_florent_>
when_entering(fsm, fsm.WRITE)?
<lekernel>
I'm also wondering how the synthesizers (which do FSM extraction and optimization) like the last_state register ...
<lekernel>
have you done some testing on that?
<_florent_>
It's working on board for my test, but I haven't look at ressources
<lekernel>
look especially at timing, FPGAs are reasonably large, but painfully slow
<_florent_>
ok I'll try to have a look at this
<_florent_>
about using the functions, what were you describing exaclty?
<_florent_>
ah sorry I miss understand your question about that
<_florent_>
the thing is that if I want to make a synchronous assignement, I'm not able to use when_* functions and will need to use an intermediary signal
<_florent_>
but I don't want to bother you with that...
<lekernel>
you can use a control signal instead
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<lekernel>
btw - if synthesizers fail to deal with the extra register correctly, then the solution is to make the FSM object insert extra "transition" states
<lekernel>
ah, he left
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<_florent_>
I have to go
<_florent_>
gn8
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<Fallenou>
slowtan 6 : lol
* Fallenou
backing up his SSD using Ubuntu ...
<Fallenou>
Ubuntu was able to repair HFS+ partition =)
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<GitHub167>
[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/S09m4Q