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<
azonenberg >
fpga_editor is terrible
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<
azonenberg >
planahead actually makes decent UIs
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<
azonenberg >
I just wish it had an option to show routing rather than just placement
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<
azonenberg >
larsc: ooh
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<
azonenberg >
very nice
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<
_florent_ >
miscope seems to work:
11:42
<
_florent_ >
now I'm going to try implementing rle...
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<
_florent_ >
thanks, now I will be able to debug the hdmi on the kc705 design ;)
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<
lekernel >
_florent_, posted it on the Milkymist twitter
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17:20
<
GitHub169 >
migen/master 9d7c679 Sebastien Bourdeauducq: genlib/fifo: simple synchronous FIFO
17:20
<
GitHub169 >
migen/master ca431fc Sebastien Bourdeauducq: fhdl/module: support clock domain remapping of submodules
17:21
* larsc
implemented a generic synchronous fifo actor yesterday
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<
lekernel >
commit early, commit often... I did check github before writing this
17:38
<
larsc >
yours is more feature complete anyway, I didn't know about the memory api
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<
GitHub194 >
milkymist-ng/master d65941d Sebastien Bourdeauducq: dvisampler: channel synchronization
17:39
<
lekernel >
heh, it's documented even
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<
larsc >
like I read the documentation ;)
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<
lekernel >
can be replaced with Q0 = D0 XOR D9, Q1 = D1 XOR D0 XOR ~D8, Q2 = D2 XOR D1 XOR ~D8, etc.
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<
lekernel >
(the right part)
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<
larsc >
you mean the if/else part?
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<
lekernel >
all that goes after "Active Data? -> TRUE"
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<
larsc >
~a xor ~b == a xor b and a xnor b == a xor b xor 1, so I guess yes
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<
kay2 >
When we have a .NGR file, what simulator could be used against it ? only XILINX products ? basically I'd like to access it via python. is there a way for that ?
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<
lekernel >
you can put the ngc (not ngr) into netgen and get a verilog netlist
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<
GitHub55 >
milkymist-ng/master 34b8388 Sebastien Bourdeauducq: dvisampler: decode before channel sync
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<
GitHub55 >
milkymist-ng/master 0376258 Sebastien Bourdeauducq: dvisampler: decoding
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