09:36 <sb0> "Testing a FIFO design for subtle design problems is nearly impossible to do. [...] Clearly the answer is to recognize that there are potential FIFO design problems and to do the design correctly from the start."

09:36 <sb0> sounds like the usual technique for FPGA stuff

09:38 <sb0> azonenberg, when do we see your upcoming excellent on-chip LA? ;)

09:38 <larsc> 'do[ing] the design correctly from the start' sounds like a good advice ;)