lekernel changed the topic of #milkymist to: Milkymist One, Migen, Milkymist SoC & Flickernoise :: Logs: http://en.qi-hardware.com/mmlogs
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<larsc> If there was crosstalk inside the fpga that would be really bad
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<larsc> the edges on the scl signal are quite spikey, depending on the hysteresis of the pin the logic might pick up a extra clock cycle
<larsc> I think it wouldn't hurt to do some extra hysteresis in the digital domain
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<wpwrak> larsc: well, it could be a synthesis problem or some odd artefact migen introduces. so not "real" crosstalk
<wpwrak> larsc: and yes, a bit of filtering may be appropriate, considering that we have signal timings that differ by no less than three orders of magnitude
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<wpwrak> an EMI filter that cuts off at, say, 1 MHz would be nice :)
<lekernel> wpwrak, hahaha, you can examine the generated verilog then :)
<lekernel> migen doesn't do anything weird with the fpga (yet)
<lekernel> build/top.v
<wpwrak> lekernel: so the finding this far don't contain anything new/unexpected for you ?
<wpwrak> findingS
<lekernel> no, I had already observed the missing ack with the saelae
<lekernel> the only new finding so far is that the level converter appears to work correctly with good signal integrity
<wpwrak> (examine verilog) one of the problems with code generators. it wouldn't exactly be the first one that hides errors in very creative new ways ;-)
<wpwrak> okay, good. i'll give the signals another look with a scope with a higher sample rate and a better probe setup (right now, the loops are very long, severely limiting the visible frequencies). see if something turns up.
<larsc> wpwrak: something like http://pastebin.com/7yDEZE9v should probably be enough to filter out spikes
<wpwrak> what do you think of outputting the state ?
<lekernel> sounds like a reasonable next step
<_florent_> hi
<_florent_> don't know it can help, but I you want to see what is going on in the FPGA, I can integrate miscope in your design.
<wpwrak> oh, "eq" is an assigment. now a few things are clearer :)
<_florent_> *If
<larsc> wpwrak: yea, we had that discussion before. I voted for assign
<lekernel> we should get python to use ordered dictionaries at all times, then we can abuse keyword arguments and use =
<wpwrak> _florent_: what i want to try is to look at the analog domain and the digital state with my MSO. that way, i don't need to guess from the digital results what exactly is happening in the analog domain at that moment
<lekernel> in addition to not having to waste time with non-determinism anymore, ever
<wpwrak> lekernel: yeah, a more python-like syntax would be nice
<wpwrak> (no non-determinism ever again) famous last words ;-)
<_florent_> wpwrak: ok
<wpwrak> wow. ISE download completed. i almost didn't believe anymore i'd live to see this :)
<wpwrak> "tar: Unexpected EOF in archive" ?!?
<wpwrak> indeed. "only" 5 GB
<wpwrak> let's try the multi-file download instead ...
<larsc> you can continue the download with wget -c
<wpwrak> Xilinx, the bloatware company ...
<wpwrak> does that work with their site ?
<larsc> yes, at least it did in the past
<larsc> you don't even need to fill out the form and everything if you already have the link
<wpwrak> didn't work :-( but let's switch to wget anyway
<wpwrak> it's funny that most web browsers make it really hard to get links to the true locations of things
<wpwrak> now .. let's undust the other scope. lower bandwidth, better sample rate
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<wpwrak> hmm, do xilinx specify a minimum input slew rate for these IOs ? I see 4 V/us for rising edges. UG381 talks a lot about output slew but not input. oh, and there's even an "I2C" I/O standard :)
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<wpwrak> lekernel: btw, while your tutorial seems to suggest that mibuild would have a setup.py, there is none
<wpwrak> hmm, so ".comb +=" is basically a post-it note for the .eq in the right-hand side to be combinatorial ?
<wpwrak> what's the default for .eq ? combinatorial, synchronized, or something else ?
<lekernel> no default - it's just an assignment, then you say when it should happen by using the corresponding special property of the Module object
<lekernel> and yes 'comb' makes it combinatorial
<wpwrak> ah "default" (tmp = x.eq(...)) gives you the reference, but doesn't add it to the design. i see.
<lekernel> yes
<wpwrak> no way to make "=" do an implicit .rd() if the right-hand side is a signal ? (i suppose the "s" in "v_led = s.rd(led)" is already contained in "led")
<lekernel> for simulation? when you have a lot of signals you can use a proxy
<lekernel> which does that
<wpwrak> what's a proxy ? :)
<lekernel> Proxy(simulator, some_object)
<lekernel> sorry, some_object_p = Proxy(simulator, some_object)
<lekernel> and then some_object_p.signal === s.rd(some_object.signal)
<lekernel> works also for writes
<wpwrak> my parser just exploded :) but yes, i see the difficulty if choosing the "right" action, given that all you know about v_led comes from its current value, which is probably not the most reliable thing to use
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<wpwrak> i.e., python would have no good way to know that the assignment is (int) var <- (Signal) expr which - if it knew - it could convert to var = design_of(expr).rd(expr)
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<lekernel> but it does for object properties, so the Proxy solution works fine - and uses wr/rd automatically
<wpwrak> it's an interesting situation: python gives you enough flexibility to implement what you want in a domain-specific language (superset), but not enough to do it with a nice syntax
<lekernel> it's also reentrant, since you store the simulator reference only in the Proxy object
<lekernel> what's wrong with the Proxy syntax? you need just one extra line to create the Proxy, then it's transparent
<lekernel> and you need to specify the simulator reference somehow anyway
<wpwrak> it's those little extra things. they're not very intuitive.
<wpwrak> ah, so the simulation is "s", not "self" ?
<larsc> python kind of mixes whether = is assignment or binding, if it is assignment it works, if it is a binding it does not
<wpwrak> what is Blinker then ?
<lekernel> s is the interface to the simulator
<lekernel> self is the module
<wpwrak> so "s" represents the simulation state ?
<lekernel> yesyou can, theoretically, have several simulators running of the same design, and they would not interfere with each other)
<lekernel> oops
<wpwrak> heh :)
<lekernel> yes. you can, theoretically, have several simulators running of the same design, and they would not interfere with each other. that's probably not a very useful feature, but it helps to understand how it's done - all the state of a given simulation is stored in s
<wpwrak> ah yes, i see. Blinker comes from before. it's the design.
<wpwrak> i think that's again a case where you have a somewhat artificial separation. the most intuitive way to think of it would be to see Blinker as a class and the simulation as an instantiation. not sure how you'd deal with multiple Blinkers in the same design, though.
<lekernel> maybe, but it worked fine like that so far
<lekernel> feel free to propose something else
<lekernel> as you can see I'm often improving the API (aka breaking compatibility)
<wpwrak> a syntax converter :)
<wpwrak> yes, i guess that happens when you find out about some python trick that allows you to go a little deeper into what the interpreter does behind the scene
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<wpwrak> nothing suspicious to see also with the other scope (besides the slew rate, which may or may not be a problem, depending on how trigger-happy the IOs are). i hope i'll find some answers in the digital domain :)
<wpwrak> ah, does migen happen have a UART that could be used for diagnostics (via the debug board) ?
<larsc> milkymist-ng has one
<larsc> and I think _florent_'s miscope also uses it
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<playthatbeat> strange, my milkymist now displays the patch title during a performance if i hit F1 to choose vid input 1
<playthatbeat> it never used to do this??!! wtf?
<Fallenou> what does F1 do?
<Fallenou> (or is supposed to do)
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<playthatbeat> it should select the composite input 1
<playthatbeat> it still DOES select input 1
<playthatbeat> video in 1
<playthatbeat> but also throws on the title of th epatch as an overlay?
<playthatbeat> f2 and f3 select inputs 2 and 3 and are fine
<playthatbeat> no title appears
<playthatbeat> this only started today, didn't do it last week
<playthatbeat> no matter, i just stick to inputs 2 and 3 for now, have to work..
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<lekernel> hi bhamilton
<GitHub68> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/2zUkjQ
<GitHub68> migen/master 75d33a0 Sebastien Bourdeauducq: fhdl/verilog/_printinit: initialize undriven Special inputs (bug reported by Florent Kermarrec)
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<wpwrak> mibuild/README: the 6 lines intro fails with "NameError: name 'counter' is not defined". if i add counter = Signal(2) (does that make sense ?) i get a bit further
<wpwrak> ah no, needs more bits
<wpwrak> is xilinx wanted to be more customer-hostile, they'd have to start mailing anthrax letters ...
<wpwrak> phew. seems i made it through license hell. until the next breakage ...
<davidc__> wpwrak: don't give them ideas.
<wpwrak> ;-)
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<wpwrak> it's very nice that mibuild takes care of the whole environment setup (or should i say "upset" ?) for the xilinx tools. that avoids all the library conflicts with the rest of the system.
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