<larsc>
lekernel: yea, they didn't want to sent them because I was flaged as an employee of competitor
<lekernel>
by the way, do you know why all those LVDS->LVCMOS converters are so slow? not realistic to have higher bitrates on single ended signals?
<larsc>
no idea
<lekernel>
SSTL (DDR etc.) is single ended and pretty fast
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<lekernel_>
it seems 24 ohm series resistors near the outputs of the max9121 improve things
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<larsc>
hm, no such thing as the empty vector :/
<lekernel_>
?
<larsc>
I want to make a core with a variable sized signal, turns out you can't make a 0 sized vector in vhdl
<lekernel_>
use migen ;) (I have to say zero-sized signals don't work either, but you can send a patch ;)
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<larsc>
maybe, someday
<larsc>
for now it is mostly working and the last step is to just add support for multiple input signals
<lekernel_>
what is it?
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<larsc>
a i2s core
<larsc>
we have a board with a couple of i2s microphones
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<Fallenou>
19:56 < lekernel> Fallenou_, has Alarm assembled the two PCBs I sent, or are those board wasted? < lekernel_ < last time I spoke with him (this week) he told me he was going to assemble them and then we could meet so that he could give me one