08:10 <lekernel> great project management from libftdi... I sent an email at the address at the beginning of the source files about the broken error reporting, and got an answer telling me to (1) use the mailing list (2) check git head (where the problem isn't fixed, either)

08:11 <Fallenou> ^^

08:11 <lekernel> ie. "I'm (1) too lazy too follow this up myself, and I (2) won't even check the git repos and simply assume you didn't"

08:12 <lekernel> and won't even update the contact info in the source, too

08:13 <kyak> at least you got a reply

08:37 <larsc> I think the first one is a reply you'd get rather often

12:50 <wpwrak> as far as (2) goes, i think statistics are in favour of that assumption :)

12:52 <wpwrak> (making diodes) nice. now you just need a transistor and then you're all set to switch from FPGAs to XXL-ASICs :)

12:54 <Fallenou> XXL toasters

12:54 <Fallenou> well, toasters can run NetBSD, don't they? :)

12:54 <wpwrak> if you time it right, you'll have no heating costs to worry about next winter :)

12:57 <Fallenou> ;)

13:48 <lekernel> hmm, the CCFL driver from my dead laptop doesn't like the plasma tube - can't generate enough voltage

13:51 <lekernel> I wonder how effective the "protection" (advertised in the control IC datasheet) against open lamp is - apparently the thing can sustain arcs in air indefinitely without tripping the protection :)

13:51 <lekernel> it only trips when the electrodes are so far apart that the arc cannot start

13:52 <lekernel> I wonder what this is supposed to protect...

15:38 <larsc> I don't get it. signal routed to one pin on the fpga http://imageshack.us/a/img16/139/fmcbclk.png signal routed to another pin http://imageshack.us/a/img23/4589/pmodbclk.png

15:39 <lekernel> it's an internal signal that you get out of the fpga, and depending on the output pin it looks different?

15:40 <lekernel> this just looks like normal transmission line ringing to me

15:40 <lekernel> one trace is probably shorter or better matched than the other?

15:42 <lekernel> if you're measuring at the pin, note that most BGA packages actually contain a bit of PCB with traces connecting the balls to the chip. but this usually only plays at higher frequencies.

15:45 <larsc> but should it be that bad, there is up to 80% overshoot, while the other looks perfect

15:53 <larsc> series resistor makes the ripple go away, maybe I'll just go with that instead of trying to figure out what's causing the effect

16:36 <lekernel> how long are your traces?

16:37 <lekernel> and have you tried using a slow slew rate?

16:37 <lekernel> SLEW=SLOW or SLEW=QUIETIO

16:38 <lekernel> remember 1ns rise time is ca. 1GHz, and you seem to be below 1ns ...

16:40 <larsc> slew is slow and drive strength is minimum

16:40 <lekernel> doesn't look that slow to me

16:40 <lekernel> the signal period is 16ns, right?

16:41 <lekernel> how different are the two traces?

16:41 <larsc> period should be 32ns

16:41 <lekernel> and how long are they?

16:41 <larsc> good question

16:41 <lekernel> power/ground plane voids can also cause impedance mismatches and this little mess

16:41 <larsc> the signals are on different IO banks

16:42 <larsc> traces should be about the same length

16:42 <larsc> going into different directions though

16:42 <lekernel> also, I believe it is safe to assume massive process (and voltage/temperature) variation on slew rate on different slowtan IO pins

16:43 <lekernel> even many things that Xilinx characterize have 300+% PVT, and AFAIR they did not characterize slew rate

16:43 <lekernel> power/ground planes can also affect trace impedance in a significant way

16:44 <lekernel> even if the traces have the same length

16:44 <lekernel> s/length/geometry

16:44 <lekernel> and power plane void = impedance mismatch on all traces that cross the void

16:45 <larsc> hm ok

16:45 <larsc> thanks

16:45 <lekernel> did you compare a second board?

16:45 <larsc> not yet

16:46 <lekernel> btw if you find some hard numbers on slowtan slew rates, I'd be happy to learn about them...

16:46 <larsc> actually my next step was to try a different board with the same fpga

16:46 <larsc> this is a series7

16:51 <lekernel> your slew rate really seems quite fast... try zooming on it using the signal that looks good

16:52 <lekernel> then you have an idea of what kind of frequency the traces are supposed to handle without excessive ringing