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lekernel>
bhamilton, btw you can ask questions here too
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bhamilton>
great :)
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GitHub87>
migen/master 7a74dae Sebastien Bourdeauducq: actorlib/spi: add DMAWriteController
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GitHub87>
migen/master fd089b1 Sebastien Bourdeauducq: actorlib/dma_asmi/OOOWriter: fix tag offset
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lekernel>
found the problem :)
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lekernel>
pairs of 2 bits were swapped ...
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lekernel>
gosh this sort of bug can be so annoying ...
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lekernel>
now the picture looks perfect
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larsc>
hm, yea that's what i expected, just couldn't figure out which two
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larsc>
which two were swapped?
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lekernel>
all pairs
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lekernel>
all 5 pairs of 2 bits in the 10-bit words
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larsc>
ha, I stopped at trying to swap at a 4 bit boundary...
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lekernel>
and no more strange behavior like lines with the wrong size etc. except at beginning and end
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larsc>
that was due to the vsync character being wrong and it thought that was data
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larsc>
actually are you sure that this is all?
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larsc>
the the vsync bit seems to be flipped
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lekernel>
updated the data
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larsc>
when I count the control character I get this
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larsc>
1237 FOUND 2 0b101010100 0b1010101011
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larsc>
4 FOUND 2 0b10101011 0b1101010100
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larsc>
1236 FOUND 2 0b1010101011 0b101010100
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larsc>
6 FOUND 2 0b1101010100 0b10101011
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larsc>
while I expect the numbers to be the other way around
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larsc>
well not count the control characters, but count the transistions of hsync on <-> hsync off
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larsc>
If vsync is off the transistion of hsync off to on should be the transition of c=0 to c=1
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lekernel>
I think so
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lekernel>
what do you see instead?
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larsc>
well a transition from c=3 to c=2
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lekernel>
hsync and vsync can have negative polarity - that's defined in EDID and enabled by default iirc
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lekernel>
maybe it's just that
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larsc>
that makes sense then
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larsc>
uhm yea, 640x480 has negative polarity for both hsync and vsync
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lekernel>
are there any modes that have positive polarity? (ie do I need to care about that, or just hardcode negative polarity?)
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larsc>
I think 720p, 1080p has positive polarity
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larsc>
negative polarity is mostly used for legacy modes, or something
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lekernel>
how is the gateware supposed to autodetect that?
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larsc>
check which character comes after de goes from high to low
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larsc>
or count the characters
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larsc>
iirc vsync and hsync polarity are actually supposed to help to distiguish between modes
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lekernel>
ok, so when de goes from high to low, it's usually hsync, and sometimes vsync+hsync ?
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lekernel>
it can never be vsync alone
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larsc>
the pattern is de nothing hsync nothing de
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larsc>
or vsync hsync+vsync vsync
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larsc>
the first symbol after de goes low will always be both hsync and vsync off
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lekernel>
ok so if c=3 immediately after de=0 then polarity is negative?
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larsc>
I'd just take the c after de=0 and xor all other c's with it
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lekernel>
good idea
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GitHub45>
milkymist-ng/master 6307331 Sebastien Bourdeauducq: dvisampler/datacapture: swap bit pairs
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GitHub91>
milkymist-ng/master 4259699 Sebastien Bourdeauducq: dvisampler: add RawDVISampler
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Fallenou>
congratz :)
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