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GitHub96 >
migen/master 0f9df2d Sebastien Bourdeauducq: genlib: add Gray counter
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GitHub96 >
migen/master fee228a Sebastien Bourdeauducq: fhdl/specials/memory: do not write address register for async reads
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GitHub96 >
migen/master 6c08cd6 Sebastien Bourdeauducq: graycounter: expose binary output
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GitHub11 >
migen/master b862b07 Sebastien Bourdeauducq: fhdl/verilog: recursive Special lowering
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GitHub11 >
migen/master e97edd7 Sebastien Bourdeauducq: genlib/fifo: disable retiming on Gray counter outputs
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GitHub11 >
migen/master 156ef43 Sebastien Bourdeauducq: genlib/cdc: add NoRetiming
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GitHub52 >
mibuild/master 85e06cc Sebastien Bourdeauducq: xilinx_ise: implement NoRetiming synthesis constraint
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GitHub9 >
milkymist-ng/master 4ff1175 Sebastien Bourdeauducq: Use the Migen asynchronous FIFO
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milkymist-ng/master d64b645 Sebastien Bourdeauducq: minimac3: move psync
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milkymist-ng/master de76faf Sebastien Bourdeauducq: Tell the Xilinx crapware that DCM_CLKGEN does not phase align, as some (but not all) of the ISE tools remark.
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GitHub61 >
milkymist-ng/master 43ac5c8 Sebastien Bourdeauducq: Remove undriven reset signals
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