<icecream95>
It seems that only depth BOs are being leaked, not colour ones
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<icecream95>
tip: when your improvement makes things worse, try doing the exact opposite thing instead
<icecream95>
shaderdb for my scheduling 'improvements': bundles in shared programs: 19694 -> 21809 (10.74%). With the opposite change, scheduling the 'worst' instructions first: 19694 -> 19609 (-0.43%)
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<alyssa>
icecream95: Uh-oh.
<alyssa>
Yeah, the way the scheduler works rn is... not good
<alyssa>
the Right approach would be to optimize *first* for register pressure via something like Sarkar, which works on multiple instructions at a time
<alyssa>
and then pattern matching that onto Midgard ALUs/etc
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<alyssa>
which would give higher cycle count in a local sense but lower register pressure so you can schedule much more aggressively --> lower cycle count
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<alyssa>
oh gosh
<alyssa>
I just accidentally emitted the code sequence "if (x == 0) { jump_to(x); }"
<alyssa>
and it... worked, no faults
<alyssa>
(on bifrost)
<HdkR>
Madness
<alyssa>
so I guess bifrost really does have indirect jumps for who knows why *blinks*
<HdkR>
Time to implement subroutines
<alyssa>
and it interprets jumps to 0 as ... what, aborting the shader maybe?
<alyssa>
otoh
<alyssa>
wait
<alyssa>
no
<alyssa>
maybe
<alyssa>
actually I thought branch offsets were from the start of the shader or something
<alyssa>
so maybe it's just infinite looping instead
<alyssa>
either way no faults :p
<HdkR>
Indirect being absolute addresses wouldn't be unheard of. Allowing you to jump between programs :P
<alyssa>
HdkR: That's horrifying.
<HdkR>
Welcome to the magic of subroutines
<alyssa>
HdkR: is that even supported in GL/CL/VK/CUDA?