00:28 <icecream95> daniels: What if I told you that rustc depends on LLVM?

00:32 <alyssa> icecream95: Dun dun dun!!!!

00:34 <alyssa> HdkR: Hey, you interested in a day job writing a compiler in Rust? 🙃

00:35 <HdkR> lol

00:37 <daniels> icecream95: apostate!

00:39 <icecream95> apostate ~ adj (very rare): 1. not faithful to religion or party or cause

00:41 <alyssa> icecream95: come join the cargo cult

00:42 <daniels> icecream95: ha

00:44 <alyssa> well, just tried piling on every non-conformant "se magic perf bit"

00:44 <alyssa> manhattan is not impressed

00:48 <alyssa> I do notice it mipmapping every frame which is a known pain point..

00:49 <daniels> what do we do for mipmap gen atm?

00:49 <alyssa> gallium's default

00:50 <alyssa> There's a cleverer way to interleave jobs but... meh. Still not clear it matters.

00:51 <alyssa> Benchmark performance just seems so *random*

00:51 <daniels> interleaving with JS _NEXT, or?

00:51 <alyssa> nah, just some job descriptor level goofiness

00:51 <daniels> ah, that

00:52 <alyssa> I infodumped to Prf_Jakob somewhere about this if you want to go crawling through logs buts mej

00:56 <icecream95> alyssa: ¿ https://freenode.irclog.whitequark.org/panfrost/2020-03-09

00:56 <alyssa> not that infodump 😉

00:58 <alyssa> icecream95: https://people.collabora.com/~alyssa/mipmap.txt

01:18 <alyssa> flags don't seem so special

01:19 <alyssa> per-sample shading, disable low/depth cull, explicit primitive restart index 0xFFFF

01:19 <alyssa> the last one is a bit baffling, that's identical to implicit for 16, but there's no index buffer at all

01:44 <cphealy_> With the midgard GPUs that support AFBC, can this compression be used for not just compressing the render buffers but also for compressing uncompressed textures upon load such that the texture loading DRAM bandwidth cost on texture sampling is reduced?

01:46 <cphealy_> I'm thinking of the case where one has a 4K GUI and the background has a 4K texture that happens not to be in a compressed texture format.

01:48 <icecream95> cphealy_: That does already happen

01:48 <cphealy_> icecream95: Is this automatic and abstracted out within the driver?

01:50 <alyssa> yes, with new mesa

01:50 <icecream95> It's automatic, and is done for every texture in a supported format that isn't updated too many times

01:51 <alyssa> daniels: https://hacks.mozilla.org/2020/10/a-new-backend-for-cranelift-part-1-instruction-selection/ <--- on linked lists in rust IRs :p

01:53 <cphealy_> excellent, thank you!

01:53 <cphealy_> Is Transaction Elimination already working with panfrost too?

01:58 <alyssa> haha

02:29 <icecream95> cphealy_: yes, https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7086

02:30 <HdkR> lol

08:33 <icecream95> The transaction elimination CRC is definitely what it says on the tin. The (reflected) polynominal is 0xeba805c967dabbc8

09:14 <icecream95> Maybe it's slightly more complicated than a CRC, as every fourth bit uses 0x22c4525cb05db48a

15:22 <B1oHazard> Hi, can anyone help me? I built mesa master and kernel with Neil bifrost patches, set env variables and got many "AS_ACTIVE bit stuck" and "gpu sched timeout" in dmesg. Using Amlogic with Mali G31.

15:23 <B1oHazard> Maybe I miss something