<icecream95>
STK now crashes with `bi_register_allocate: Assertion `success' failed.`
<alyssa>
uh oh
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<icecream95>
alyssa: I suspect the problem is related to ~~DNS~~ texture instructions as usual
<alyssa>
:|
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<icecream95>
I wonder if this might just be a bug with spilling
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<icecream95>
STK doesn't work with BIFROST_MESA_DEBUG=nosched as cubeface lowering isn't done. If I move the lowering up in bi_take_instr, it then crashes on assert(!now->regs.slot23.slot2)
<macc24>
hold up, BIFROST_MESA_DEBUG?
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<icecream95>
alyssa: I think "if (l->alignment[i] == 0) continue;" should be added to the loop in lcra_get_best_spill_node, so that RA fails instead of trying to spill nodes that don't exist
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<alyssa>
icecream95: Oh, I didn't consider the interaction of nosched with cubefaces.
<alyssa>
The slot23.slot2 thing is a legitimate bug which I found and fixed last night, MR incoming.
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<alyssa>
bbrezillon: fwiw, Midgard architecturally can't support anything higher than Vulkan 1.0 since there's no way to do subgroups
<alyssa>
[Bifrost comes with BRANCHC, lane ID in FAU, and CLPER, which together form the needed building blocks to do subgroups.]
<amonakov>
alyssa: please elaborate, I thought all subgroup primitives are optional?
<bbrezillon>
alyssa: noted
<alyssa>
amonakov: if so, disregard my comment
<alyssa>
well. everything about the hw is true. midgard can't do it, bifrost can.
<alyssa>
also, some of the fancier stuff *might* need v7 at that (all the extra CLPER flags)
<amonakov>
re-reading the spec, it appears "basic" subgroup ops are mandatory to implement, rest are optional
<alyssa>
amonakov: Ack. Midgard doesn't even have a way to do basic ones...
<alyssa>
Derivative support is a giant hack :p
<alyssa>
[There's support derivative support in the texture pipe for LOD computation, so they bolted on dFdx/dFdy instructions to the texture pipe.]
<alyssa>
Aside: it occurs to me subgroup ops could be super useful for computer vision stuff
<amonakov>
on Midgard, does Mesa map 4 SPIR-V execution contexts to 1 VLIW hw context, or?..
<alyssa>
?
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<amonakov>
your "?" confused me
<amonakov>
anyway, maybe a silly question (I think the answer is "it does not")
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<amonakov>
by any chance, is there any discussion of Bifrost cache hierarchy and access speed out there? I think I know what to expect, but I'd happy to be surprised
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<alyssa>
I don't think that's documented but I'd also be happy to be surprised
* alyssa
tries to implement copyprop
<alyssa>
cause I don't think I can do real work rn :p
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<alyssa>
also, need to really figure out which is worse between copyprop supporting partial writes, or going back to pseudoinstruction COMBINE lowerings..
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<alyssa>
ok, have a UBO pushing implementation for Bifrost too
<alyssa>
let's see what deqp thinks
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* alyssa
bug hunts
<alyssa>
note to self: need a pseudo-instruction for handling fabs/fneg optimally (*FADD x, #0 vs +FMAX x, x both work for 32-bit)
<alyssa>
16-bit has less luck
<alyssa>
for clamp at least
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<cwabbott>
alyssa: don't forget it has to be FADD x, -0 to get the sign of 0 correct :)
<alyssa>
cwabbott: thank you for your patch ;P
<cwabbott>
don't worry, you'll have to write it once you support vulkan and VK_KHR_shader_float_controls
<alyssa>
cwabbott: Oh, alright, we're not supporting Vulkan though right?
* alyssa
glares at bbrezillon ;p
<amonakov>
so many control bits, but a bit to request correctly-rounded FMA ain't one of them (matters on amdgpu)
<alyssa>
rip
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<icecream95>
Now STK (with nosched) hits an infinite loop while scheduling
<alyssa>
Uhh
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