Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Lofty> Ping Sarayan
<Sarayan> pong
<Sarayan> pong lofty even
<Lofty> <Lofty> Sarayan: I'm reading through the diagram, and there's no way to get a combinational sum output
<Lofty> <Lofty> That...looks wrong
<Sarayan> combinational sum?
<Lofty> As in, the output of the adder to a combinational output
<Lofty> *the sum output
<Sarayan> you mean feed the sum output to the input of a lut?
<Lofty> There's no way to get from S to an output without going through the flop
<Sarayan> hmmm interesting
<Lofty> Oh. And looking at it, your flop diagram is also missing flop-enable inputs
<Sarayan> they're "integrated" in the clk input
<Lofty> ...Ah. That's fun.
<Sarayan> the 3 clock lines are clock/enable pairs
<Sarayan> indeed
<Lofty> I guess it makes a change to the "mux connected to self" approach
<Sarayan> the muxes in front of the output, [TB]FF{0,1,1L}, their selections are "reg" and "nlut". I suspect that yes, the sum always goes to the ffs
<Sarayan> I'm not 100% sure though, and the quartus schem doesn't say iirc
<Lofty> Sarayan: but if you instantiate a combinational adder, it selects NLUT as the output
<Sarayan> Oh?
<Sarayan> cool
<Sarayan> and arith_sel is on "adder"?
<Lofty> Yep
<Lofty> Here's my suspicion
<Lofty> The path which is direct from the LUT on your diagram
<Sarayan> tehn I guess it's the output of the adder/lut mux that goes to the end muxes
<Lofty> Should actually be from after arith_sel
<Lofty> Yeah
<Sarayan> we agree
<Lofty> Since the flops have no latch mode, right?
<Sarayan> nope
<Sarayan> only edge
<Lofty> Okay, good to get that resolved
<Sarayan> .jmi
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<Sarayan> Lofty: The figure 1-5 page 1-6 of cv_5v2.pdf confirms our idea
<Lofty> Okay, good
<Sarayan> Fixed the svg, regenerated the docs
<Lofty> Thank you
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