14:59 <Lofty> Sarayan: what do you think of the diagram, though?

15:26 <Sarayan> It's nice

15:27 <Sarayan> I wonder which of the two is the best in a setup with the actual configuration active, like quartus does

15:28 <Sarayan> since a lot of te lines essentially dossepear

15:28 <Sarayan> sorry, cat stole an arm

15:28 <Lofty> Cats tend to do that

15:28 <Lofty> I think in that situation it's not too tricky to highlight the flying wires that I'm using to reduce visual noise

15:29 <Sarayan> true

15:29 <mwk> can confirm, nothing like a good borrowed arm to rest on

15:29 <Sarayan> in any case, it's much better than the quartus one because all is on there

15:30 <Lofty> I mean, the mode mux could be something to expand upon

15:32 <Sarayan> It's probably splittable bit we need to trigger the last 4 modes to be sure

15:33 <Sarayan> it's 8 bits (which is still better than the quartus original which is 14 iirc)

15:33 <Lofty> Mhm

15:33 <Sarayan> arith is folded in otherwise, and I'm not sure what else

15:34 <Lofty> Sarayan: something daveshah mentioned is that Quartus might have its own intra-ALM routing data

15:34 <Sarayan> For inner blocks it looks harcoded

15:34 <Sarayan> for peripheral it indeed is explicit

15:35 <Sarayan> I have to complete clock mux maps in a notes file thanks to thar, I'll need to add them to the code and the doc at some point

15:36 <Lofty> Mmm

15:36 <Lofty> Also it was suggested that I try generating the intra-ALM routing from the diagram :P

15:36 <Sarayan> I choose to only have the real routing in the graph because it's closer to reality and because I don't want to force quartus' choices

15:37 <Sarayan> mistral is already a pile of code generators, wgat's another one between friends

15:38 <Sarayan> cat is actually dreaming on my arm

15:38 <Lofty> Only the finest of metametaprogramming here /s

15:39 <Lofty> To be fair, like libtrellis instead enforces its own design decisions on its users

15:39 <Lofty> But the only real user is nextpnr-ecp5 :P

15:46 <Lofty> Sarayan: I think something useful would be if we could decompile a bitstream into Verilog cells

15:46 <Lofty> e.g. icebox_vlog I think

15:47 <omnitechnomancer> and the bitfile packer but that is in libtrellis

15:48 <Sarayan> You probably could do that from the deocmp output

15:48 <Sarayan> decomp

15:50 <Sarayan> not especially hard for the parts we understand, I think

15:50 <Sarayan> if you try to generate quartus-compatible verilog you may even want to generate forced placements

15:54 <Sarayan> but, hmmm, perhaps generating it from the library is even easier, it already has the route solver after all

15:55 <Sarayan> the funkiest part is going to go from lut table to boolean equations I'm sure