Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
<omnitechnomancer> You could either use just a sim model of the LUT or use the same code that trellis uses to generate the logic expressions the vendor tools want for LUT init from lut bits
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