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<tnt>
Lofty: huh, I found OpenROAD quite easy to build, it was pretty much seamless (compared to says the quicklogic arch defs for vtr ...)
<tnt>
For the PDK I just call the python script myself ... need to workout of to extricate the build system from conda.
<tnt>
s/of/how/
<Lofty>
tnt: KLayout is painful to build and install
<tnt>
Oh yeah, I was mostly talking about the actual openroad-flow repo with the 3 tools (yosys/openroad/tritonroute)
<tnt>
klayout was mostly just big and slow to build ... also the make install just put everything in the same directory, libraries/binaries/.... just all dumped there.
<Lofty>
And then the actual KLayout binary doesn't load
<tnt>
huh, didn't have that issue.
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<nickoe>
mithro: By the way, was my answer about eeschema from yesterday good enough? :S
<Lofty>
What are the power/ground driver cells in sky130_fd_sc_hd?
<Lofty>
tap et al seem to be sinks, rather than sources
<tnt>
what do you mean driver cells ?
<tnt>
There is the various 'pin' layers that tell the routing tool where it needs to connect stuff to.
<Lofty>
tnt: Yosys has hilomap for VCC/GND cell connections, right?
<Lofty>
So to use it it would need a constant-1 that corresponds to a voltage driver
<Lofty>
And a constant-0 that corresponds to a ground
<tnt>
Yeah, I saw that but I don't see why that would be needed.
<tnt>
you can just wire the input pin right to the power rail that's next to it.
<tnt>
I think the hilomap is not for power connections, it's for the 'contants' like logic inputs of a cell that are fixed.
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<Lofty>
Which are equivalent to power connections
<Lofty>
At least logic power connections
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<tnt>
yeah, and I see a use for that in say ... a FPGA where you dedicate a lut to drive '1' and one to drie '0'.
<tnt>
But here I don't see why you'd need a cell to do that. just wire the input to the power rail.
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<tnt>
(and yeah, tap* are definitely sinks, they are the special cells that will properly bias the mos bulk (both p-substrate and n-well). They need to be injected by the placer periodically so that there is no more than 150u (IIRC) between any transistor and the bulk connection.
<Lofty>
Interesting, though at the moment I'm just playing around with a boring Yosys flow
<tnt>
err 15um actually not 150u :p
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