08:33 <Lofty> Are you allowed to mix and match cells for the final product? e.g. using hs cells in critical paths and hd elsewhere?

08:36 <tnt> Not all cells libraries have the same grid structure, so you can't really mix them on the same grid.

08:36 <tnt> But if you have a components that needs to be faster, you can make it a macro with its own grid and include it that way.

08:40 <Lofty> Hmm...

08:40 <tnt> Yeah hs/hd don't have the same height ...

16:55 <mithro> Lofty: I think the hs/ms/ls all have the same height

16:59 <Lofty> So those cells can be mixed, mithro?

17:21 <mithro> Lofty: My understanding is yes but I only have a basic understanding

17:58 <tnt> Lofty: not sure why you would really though ...

17:59 <tnt> I mean the LS are not smaller than the HS, they just use different implant for tweaking the Vt of the NMOS/PMOS to be lower power / lower leakage.

18:01 <tnt> looking at a few cells of those libs, they seem to be specifically designed to have the same layout so you can swap them between libs after placement / possibly even routing.

22:26 <mkk_> [Trevor Clarke, skywater-pdk] https://opencores.org/projects?expanded=Uncategorized&asicProven=true

22:27 <mkk_> [Trevor Clarke, skywater-pdk] just a link for anyone looking for ideas to tape out and test...those are all the ASIC proven cores on opencores...would be a good starting place for sky130 cores

22:31 <Lofty> I've been working on a chess move generator I wrote a little while back; doubt it will make it into the shuttle, but it's an interesting synthesis benchmark

22:31 <Lofty> Very high signal fanout, very wide buses