17:13 <mkk__> [Tim Edwards, skywater-pdk] @Iztok Jeras: I have called it an "all-digital PLL" but actually it is an all-digital frequency-locked loop. I can post the design files including the ngspice netlists for simulation.

18:01 <mkk__> [Tim 'mithro' Ansell, skywater-pdk] @Tim Edwards Any idea why you haven't done that already?

18:01 <mkk__> [Iztok Jeras, skywater-pdk] yes please

18:01 <mkk__> I did read the comments so I do know it is a frequency-locked loop

18:02 <mkk__> [Iztok Jeras, skywater-pdk] Is this the same PLL/DLL to be used in the template (I think you call it harness)?

18:07 <mkk__> [Iztok Jeras, skywater-pdk] If you look at the separate thread above, I was able to run openlane builds for the PLL and I tried to use the inverter to refresh my spice knowledge. I found an issue I will report (of course it is possible I did something wrong).

19:29 <mkk__> [Mitch Bailey, skywater-pdk] Here is a script that will list the mag cells with port conficts.

19:29 <mkk__>   

19:29 <mkk__> ```#! /bin/bash

19:29 <mkk__> awk '

19:29 <mkk__> /label/ {

19:38 <mkk_> [Tim 'mithro' Ansell, skywater-pdk] @Mitch Bailey I wonder if we can add that to the skywater-pdk CI in some way?

19:48 <mkk_> [Mitch Bailey, skywater-pdk] @Tim 'mithro' Ansell Sorry, I posted in the wrong channel. Was supposed to be in a private conversation.

19:52 <mkk_> [Tim 'mithro' Ansell, skywater-pdk] @Mitch Bailey That sounds like something which should be in a public conversation? The more we share how people are doing things the more we all learn!

19:52 <mkk_> [Tim 'mithro' Ansell, skywater-pdk] Plus finding mag cells with port conflicts sounds like a pretty useful thing to be doing.

20:59 <mkk_> [Tim 'mithro' Ansell, skywater-pdk] @matt venn Is live right **now** talking about going zero to ASIC at https://www.twitch.tv/hackadaytwo