03:38 <mkk_> [Anton Dyudin, skywater-pdk] So forgive me if this is always the first thing anyone thinks of

03:38 <mkk_> Or are you just always going to be better off with "hefty GPU"

03:38 <mkk_> but have any ASICs been designed to accelerate OpenLANE routing layout etc algorithms?

03:39 <mkk_> [Anish S, skywater-pdk] too rapidly-changing for ASIC to be worth it afaik

03:39 <mkk_> [Anish S, skywater-pdk] doing it on an FPGA might be interesting though

03:52 <mkk_> [Anton Dyudin, skywater-pdk] What sort of hot loop do you end up spending 80% of your clock time in, anyway? Like, https://docs.google.com/presentation/d/e/2PACX-1vRtwZPc8ykkkgtUkHkoJZrP9jKOo3FYdKqbg-So0ic6_kx7ha1vHnxrWmuxWkTc9GfC8xl0TfEpMLwK/pub?slide=id.g8a122ff1a1_6_880 certainly looks like something you throw TensorFlow at, but wouldn't know if it was chosen for being a significant chunk of compute vs being um visually compelli

05:00 <mkk_> [Kunal Ghosh, skywater-pdk] This was so unexpected and is so inspirational for learners like me. Thanks Steve Hoover for sharing such an excellent blog. *This year really has been full of surprises*

05:00 <mkk_> https://www.vlsisystemdesign.com/13-year-old-nicholas-sharkey-creates-a-risc-v-core/