08:44 <kgugala> Morning mithro

11:50 <mkurc> Morning

11:50 <mkurc> I need some advice

11:50 <mkurc> I am trying to migrate all VPR related stuff out of Yosys

11:51 <mkurc> I want to have a common flow for Vivado and VPR up to some point:

11:51 <mkurc> Verilog -> synthesis(yosys) -> edif -> Vivado

11:52 <mkurc> and Verilog -> synthesis(yosys) -> techmap(in yosys) -> blif -> VPR

11:52 <mkurc> The problem is that i need to map $alu to a chain of CARRY4 which are understandable by Vivado

11:52 <mkurc> and it works

11:53 <mkurc> However, I cannot map CARRY4 to a chain of CARRY0 + 3xCARRY which are understandable by VPR

11:53 <mkurc> CARRY0 and CARRY have separate output ports for carry chain and fabric

11:54 <mkurc> and the Vivado's CARRY4 does not. It only has a "general" output. I guess that Vivado infers it later (after loading EDIF netlist) whether to connect it to fabric or carry chain.

11:55 <mkurc> So it seems that removing VPR stuff from Yosys completely is not possible.

11:55 <mkurc> Either we will have some VPR stuff in Yosys or we implement inference of carry chain connections in VPR (right?)

11:58 <mkurc> Also the CARRY4 does not allow direct control of the chain intialization mux. It must also be inferred in Vivado

16:28 <mkurc> I've confirmed that xc7/tests/counter does not work from latest master branch (4b66516). I've created a related issue on Github - #382

19:07 <elms> litghost: I have a iCE40 fasm file https://gist.github.com/elmsfu/e5383b543934a58e6f376a9d133283c9 Please comment on the gist with any feedback.

19:07 <tpb> Title: iCE40 FASM · GitHub (at gist.github.com)