01:29 <mithro> litghost: https://github.com/SymbiFlow/prjxray-db/compare/master...mithro:master

01:30 <tpb> Title: Comparing SymbiFlow:master...mithro:master · SymbiFlow/prjxray-db · GitHub (at github.com)

01:39 <litghost> That looks good

01:54 <mithro> litghost: Great! Pushed

05:29 <litghost> symbiflow-arch-defs can now place and route a working Murax (https://github.com/SpinalHDL/VexRiscv#murax-soc) on a basys3! TDP BRAM 18k are testing both 8 and 16bit wide!

05:29 <tpb> Title: GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation (at github.com)

05:29 <litghost> Instructions are https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/soc_tests/murax/README.md

05:29 <tpb> Title: symbiflow-arch-defs/README.md at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)

12:07 <sf-slack> <kgugala> litghost: this is absolutely awesome!!

21:42 <sorear> (can someone summarize exactly what the new development is? best guess: using only free tools, can build muraxsoc as a partial reconfiguration bitstream, still need vendor tools for the "outer" bitstream with I/Os)

22:44 <litghost> Sorear: exat

22:45 <litghost> Exactly

22:45 <litghost> Next step is getting picosoc working

22:45 <litghost> The IOB and clock network definition, to remove the outer bitstream

22:45 <litghost> Then*

22:45 <sorear> And the “new” part is … BRAMs?

22:48 <litghost> From the outside, ya