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<litghost>
hackerfoo: It would be good to trace the routing path from the IOB and find where the "break" is located
<litghost>
xc7/utils/prjxray_find_inode.py is wire string -> inode / connection db and xc7/utils/prjxray_lookup_inode.py provide inode -> wire string / connection db
<litghost>
hackerfoo: So make sure VPR can route from the wire after the IOI tile to the inode in question
<litghost>
hackerfoo: If that works, then route from the IOB inode to the IOI wire
<litghost>
hackerfoo: The problem is either IOB pb_type -> IOI wire, or IOI wire to general fabric
<hackerfoo>
litghost: Okay, thanks
<sf-slack2>
<mkurc> hackerfoo: Are you importing ILOGIC site along with IOI3 tiles? I'm asking as there is no direct route from IOB to the fabric. You have to route through the ILOGIC site.
<hackerfoo>
mkurc: Yes
<sf-slack2>
<mkurc> Ok
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<sf-slack2>
<kejace> I tried replicating this for the arty. I'm now getting a similar error
<sf-slack2>
<kejace> And on a second attempt ```PYTHONPATH=../symbiflow-arch-defs/utils python3 ../symbiflow-arch-defs/xc7/utils/prjxray_create_ioplace.py --pcf basys3.pcf --map ../symbiflow-arch-defs/build/xc7/archs/artix7/devices/xc7a50t-arty-roi-virt/synth_tiles_pinmap.csv --blif counter.eblif --out counter_io.place PCF constraint "set_io clk W5" from line 2 constraints pad W5 which is not in available pad map: A9 C2 D10 E3 GND T10 VCC
<tpb>
Title: VTR cannot handle clustering of multiple atoms of the same type · Issue #250 · SymbiFlow/vtr-verilog-to-routing · GitHub (at github.com)
<sf-slack2>
<kgugala> @mithro I updated the #250 issue on github
<sf-slack2>
<kejace> @litghost thanks, I got it to compile and build this way and although all of the LEDs light up and they don't blink, I think that I can work on a ClaSH example from here on
<litghost>
kejace: You might want to start with a sanity check example, e.g. buttons (tie sw[0] to led[0], etc)
<litghost>
kejace: I've mostly been testing on basys3 because it has more LED's and buttons, so it possible that something is wrong with the arty flow
<hackerfoo>
litghost: Also for the other key, so neither RR node is in the map.
<litghost>
hackerfoo: The map only has IPIN/CHANX/CHANY/OPIN
<litghost>
hackerfoo: Not SINK/SOURCE
<litghost>
hackerfoo: And the error prints SINK/SOURCE
<hackerfoo>
Can I look those up somewhere?
<litghost>
hackerfoo: You can grep the rrgraph to walk from SINK to an IPIN (and SOURCE to OPIN)
<hackerfoo>
Okay
<litghost>
hackerfoo: The rrgraph by default has no whitespace, I use "xmllint --format in.xml > out.xml" to aid grepping
<hackerfoo>
Thanks. I was trying to find a way to do something like that.
<sf-slack2>
<kejace> I'm navigating the Makefile to understand why the pinmap is so small ```web-scale ➜ symbiflow-simple-sample git:(master) ✗ cat ../symbiflow-arch-defs/build/xc7/archs/artix7/devices/xc7a50t-arty-roi-virt/synth_tiles_pinmap.csv name,x,y,z,is_clock,is_input,is_output E3,42,26,0,1,1,0 C2,79,24,0,0,1,0 A9,9,49,0,0,1,0 T10,9,5,0,0,0,1 D10,9,3,0,0,0,1 VCC,22,25,0,0,1,1 GND,35,26,0,0,1,1```
<sf-slack2>
<kejace> For example, they correspond to the following from (https://github.com/Digilent/vivado-boards/blob/master/new/board_files/arty-a7-35/E.0/part0_pins.xml) ``` <pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/> <pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/> <pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/> <pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
<sf-slack2>
<pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>```
<sf-slack2>
<kejace> Let's say I wanted to add `<pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>`
<sf-slack2>
<kejace> What file should I edit?
<sf-slack2>
<kejace> I guess this relates to `hackerfoo`'s comment above ```Oddly, only the unbonded IO pads are present in the arch.xml. hackerfoo (IRC)APP [8:54 PM] Ah, they are probably being removed since they are in synth_tiles.json.```