<hackerfoo> Getting closer. I was able to generate rr_graph.real.xml. Now I need to fix this: PCF constraint "set_io in[0] V17" from line 2 constraints net in[0] which is not in available netlist: in, out
<hackerfoo> Hopefully not too much more to go.
<hackerfoo> V17 isn't one of the pins I selected (W2/3 & V2/3)
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<litghost> hackerfoo: What target are you running
<litghost> hackerfoo: The current process is sdc -> ioplace
<litghost> pcf*
<tpb> Title: symbiflow-arch-defs/arch_define.cmake at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<hackerfoo> litghost: buttons_basys3_x1y0_fasm
<litghost> hackerfoo: Did you update basys3.pcf?
<litghost> Or make a new pcf for the x1y0 test?
<hackerfoo> Yeah
<litghost> Which? And did you update the CMake description of the test to use the correct file?
<hackerfoo> I just modified the existing one. I'll make a separate one when it works.
<litghost> hackerfoo: The error matches the pcf file located in master (https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/tests/buttons/basys3.pcf)
<tpb> Title: symbiflow-arch-defs/basys3.pcf at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<litghost> hackerfoo: Which path did you edit?
<hackerfoo> That was before I modified the PCF.
<litghost> Ah, sure
<hackerfoo> Still fails the same way, though.
<hackerfoo> The netlist is missing from the eblif, I think.
<hackerfoo> Or net.
<litghost> hackerfoo: I'm guess, but I think it's because the new design no longer has a bus
<litghost> hackerfoo: e.g. input [0:0] in -> set X in, versus input [1:0] in -> set X in[0]
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<hackerfoo> I see
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<hackerfoo> Now the pads are missing from synth_tiles_pinmap.csv
<hackerfoo> I think I need to add a way of locating real pads, because they were previously synthetic tiles.
<hackerfoo> Maybe I can still add them to synth_tiles.json
<tpb> Title: prjxray-db/xc7a35tcpg236-1_package_pins.csv at master · SymbiFlow/prjxray-db · GitHub (at github.com)
<hackerfoo> litghost: Thanks, that looks useful.
<hackerfoo> I'm adding code to prjxray_create_synth_tiles.py to add an entry for each IOPAD, similar to GND & VCC.
<hackerfoo> I should probably just try changing the JSON manually first.
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<hzeller[m]> While at it, I might be interested in U2, U4, U5, U7, U8, V4, V5, V7, V8, W4, W6, W7 :) (7-segment things in Basys3)
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<hackerfoo> litghost: What consumes synth_tiles_pinmap.csv?
<tpb> Title: symbiflow-arch-defs/arch_define.cmake at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<mithro> litghost: I needed this patch to make the harnesses build successful.... https://www.irccloud.com/pastebin/0LucohTl/
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<tpb> Title: Comparing master...new-master · SymbiFlow/prjxray-db · GitHub (at github.com)
<litghost> Ya
<mithro> litghost: Still looks like there is some issues with the kintex with missing IOI_LEAF_GCLK0, IOI_IOCLK0 and similar?
<litghost> mithro: Ya, https://github.com/SymbiFlow/prjxray/pull/1017 is attempting to fix it
<tpb> Title: Avoid failing on empty pip lists (which may occur). by litghost · Pull Request #1017 · SymbiFlow/prjxray · GitHub (at github.com)
<litghost> mithro: I think I have the last fix in
<hzeller[m]> What are the premap..v verilog files generated by yosys used for https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/yosys/synth.tcl#L7 ? It does not seem to be needed for the remaining vpr process (I comment them out in symbiflow-simple-sample). I suspect this is just used as a debugging output but it is not something needed in a typical workflow ? Or, in other words: can I assume that input verilog
<hzeller[m]> output eblif is what typically is needed in a workflow invoking yosys ?
<tpb> Title: symbiflow-arch-defs/synth.tcl at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)
<litghost> hzeller: The premap files can be used to feed Vivado after unmapping some VPR specific flows
<litghost> hzeller: This allows some A/B comparisions between VPR and Vivado post-synth
<litghost> hzeller: Going from the fully mapped output is non-trival, so we write out the verilog premapping
<hzeller[m]> ah ok, but for just using the FOSS toolchain it is not needed
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<litghost> true
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<mithro> litghost: DB pushed