01:33 <hackerfoo> Getting closer. I was able to generate rr_graph.real.xml. Now I need to fix this: PCF constraint "set_io in[0] V17" from line 2 constraints net in[0] which is not in available netlist: in, out

01:33 <hackerfoo> Hopefully not too much more to go.

01:34 <hackerfoo> V17 isn't one of the pins I selected (W2/3 & V2/3)

15:46 <litghost> hackerfoo: What target are you running

15:46 <litghost> hackerfoo: The current process is sdc -> ioplace

15:46 <litghost> pcf*

15:48 <litghost> https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/make/arch_define.cmake#L45

15:48 <tpb> Title: symbiflow-arch-defs/arch_define.cmake at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)

15:49 <hackerfoo> litghost: buttons_basys3_x1y0_fasm

15:55 <litghost> hackerfoo: Did you update basys3.pcf?

15:55 <litghost> Or make a new pcf for the x1y0 test?

15:56 <hackerfoo> Yeah

15:57 <litghost> Which? And did you update the CMake description of the test to use the correct file?

16:01 <hackerfoo> I just modified the existing one. I'll make a separate one when it works.

16:02 <litghost> hackerfoo: The error matches the pcf file located in master (https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/tests/buttons/basys3.pcf)

16:02 <tpb> Title: symbiflow-arch-defs/basys3.pcf at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)

16:03 <litghost> hackerfoo: Which path did you edit?

16:03 <hackerfoo> That was before I modified the PCF.

16:03 <litghost> Ah, sure

16:03 <hackerfoo> Still fails the same way, though.

16:04 <hackerfoo> The netlist is missing from the eblif, I think.

16:04 <hackerfoo> Or net.

16:06 <litghost> hackerfoo: I'm guess, but I think it's because the new design no longer has a bus

16:07 <litghost> hackerfoo: e.g. input [0:0] in -> set X in, versus input [1:0] in -> set X in[0]

17:19 <hackerfoo> I see

19:36 <hackerfoo> Now the pads are missing from synth_tiles_pinmap.csv

19:43 <hackerfoo> I think I need to add a way of locating real pads, because they were previously synthetic tiles.

19:44 <hackerfoo> Maybe I can still add them to synth_tiles.json

20:00 <litghost> hackerfoo: You looking for https://github.com/SymbiFlow/prjxray-db/blob/master/artix7/xc7a35tcpg236-1_package_pins.csv by any chance?

20:00 <tpb> Title: prjxray-db/xc7a35tcpg236-1_package_pins.csv at master · SymbiFlow/prjxray-db · GitHub (at github.com)

20:01 <hackerfoo> litghost: Thanks, that looks useful.

20:02 <hackerfoo> I'm adding code to prjxray_create_synth_tiles.py to add an entry for each IOPAD, similar to GND & VCC.

20:04 <hackerfoo> I should probably just try changing the JSON manually first.

20:22 <hzeller[m]> While at it, I might be interested in U2, U4, U5, U7, U8, V4, V5, V7, V8, W4, W6, W7 :) (7-segment things in Basys3)

22:50 <hackerfoo> litghost: What consumes synth_tiles_pinmap.csv?

22:51 <litghost> https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/make/arch_define.cmake#L45

22:51 <tpb> Title: symbiflow-arch-defs/arch_define.cmake at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)

23:25 <mithro> litghost: I needed this patch to make the harnesses build successful.... https://www.irccloud.com/pastebin/0LucohTl/

23:25 <tpb> Title: Snippet | IRCCloud (at www.irccloud.com)

23:40 <mithro> litghost: This look good? https://github.com/SymbiFlow/prjxray-db/compare/new-master?expand=1

23:40 <tpb> Title: Comparing master...new-master · SymbiFlow/prjxray-db · GitHub (at github.com)

23:40 <litghost> Ya

23:43 <mithro> litghost: Still looks like there is some issues with the kintex with missing IOI_LEAF_GCLK0, IOI_IOCLK0 and similar?

23:44 <litghost> mithro: Ya, https://github.com/SymbiFlow/prjxray/pull/1017 is attempting to fix it

23:44 <tpb> Title: Avoid failing on empty pip lists (which may occur). by litghost · Pull Request #1017 · SymbiFlow/prjxray · GitHub (at github.com)

23:44 <litghost> mithro: I think I have the last fix in

23:48 <hzeller[m]> What are the premap..v verilog files generated by yosys used for https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/yosys/synth.tcl#L7 ? It does not seem to be needed for the remaining vpr process (I comment them out in symbiflow-simple-sample). I suspect this is just used as a debugging output but it is not something needed in a typical workflow ? Or, in other words: can I assume that input verilog

23:48 <hzeller[m]> output eblif is what typically is needed in a workflow invoking yosys ?

23:48 <tpb> Title: symbiflow-arch-defs/synth.tcl at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)

23:49 <litghost> hzeller: The premap files can be used to feed Vivado after unmapping some VPR specific flows

23:49 <litghost> hzeller: This allows some A/B comparisions between VPR and Vivado post-synth

23:49 <litghost> hzeller: Going from the fully mapped output is non-trival, so we write out the verilog premapping

23:50 <hzeller[m]> ah ok, but for just using the FOSS toolchain it is not needed

23:50 <litghost> true

23:55 <mithro> litghost: DB pushed