05:39 <sf-slack2> <justidl3> Thanks for the help. I currently have a pynq v1 board, which happens to use the same fpga logic chip as the zedboard. As of now, what is the best approach for porting boards with the same xilinx chip?

05:39 <sf-slack2> <justidl3> Also, is it better to use the slack or irc channel? Just wondering

06:30 <sf-slack2> <kgugala> @justidl3 we have a bot that routes messages between Slack and symbiflow IRC channel, so you can use whatever is more convenient for you

06:31 <sf-slack2> <kgugala> As for your first question:

06:31 <sf-slack2> <kgugala> you have zynq 7020

06:31 <sf-slack2> <kgugala> this part is not in our main focus (we support 7010)

06:32 <sf-slack2> <kgugala> however you can try to create part definition in prjxray https://github.com/SymbiFlow/prjxray/tree/master/settings

06:32 <tpb> Title: prjxray/settings at master · SymbiFlow/prjxray · GitHub (at github.com)

06:33 <sf-slack2> <kgugala> here is the definition for 7010 https://github.com/SymbiFlow/prjxray/blob/master/settings/zynq7.sh

06:33 <tpb> Title: prjxray/zynq7.sh at master · SymbiFlow/prjxray · GitHub (at github.com)

06:33 <sf-slack2> <kgugala> you'd need to recreate the whole database (run all the fuzzers)

06:33 <sf-slack2> <kgugala> this may take some time

06:33 <sf-slack2> <kgugala> and, of course, you may need to fix some bugs :slightly_smiling_face:

08:32 <markus-zzz> Using nextpnr-ecp5 --gui (built from git a few days ago) I am not able to see any of the nets in my design. I have tried right-clicking on entries in the 'Nets' tab and 'Highlight' but nothing shows. Am I doing it wrong or simply misunderstanding something?

08:32 <daveshah> Is the design routed?

08:33 <markus-zzz> yes it is routed

08:33 <markus-zzz> (otherwise nothing should show in the 'Nets' tab right?)

08:34 <daveshah> Nets are a netlist entity, so they show in the nets tab as soon as the design is loaded

08:36 <markus-zzz> ah, right. yes of course. But anyway routing is done according to the tool.

08:39 <daveshah> Not sure what is happening, seems to work fine for me

08:40 <daveshah> Are you on a relatively recent nextpnr, there was a bug that caused the "cells" and "nets" tabs to swap a while ago?

08:40 <markus-zzz> I am on ff958830

08:40 <daveshah> Oh, you are on ECP5 not ice40

08:41 <daveshah> There's no graphic data for the ECP5 routing yet

08:41 <daveshah> Never got round to doing that

08:41 <markus-zzz> aha, well then that explains :)

08:42 <markus-zzz> Would it be something difficult to do that? What steps would it involve?

09:21 <daveshah> markus-zzz: I think we might need to fix some performance issues first

09:21 <daveshah> The bigger ECP5s have quite a bit of routing to show

09:22 <daveshah> But basically it would be a case of adding "Decal" structures describing lines to all the wires

09:24 <markus-zzz> Right, I looked around a bit at how ice40 does it but maybe the drawing framework needs to be redesigned a bit to handle much bigger FPGAs as you say.

09:25 <markus-zzz> just looking for something that I could possibly help out with.

09:32 <daveshah> If you are interested in this, the first thing I'd play with is adding a switchbox (just a rectangle in the middle of the tile) and some stub wires

09:32 <daveshah> Don't need to get all the tiles connected up, just have short stubs for each wire

09:32 <daveshah> This will provide a place to start and also test the performance a bit

09:34 <markus-zzz> yeah, that is probably a good approach. I will try to find some time to play around with it.

16:55 <Kergadon> Hello, I am interested in helping out with this project. I have experience with python and, limited experience with verilog. I have the ecp5-5g versa dev board, so that is what I'd like to focus on at least at the start.

16:56 <Kergadon> Also would switching over to slack be preferable?

17:44 <sf-slack2> <pgielda> It does not matter, there is a bot that moves messages both ways

17:45 <sf-slack2> <pgielda> So whatever works for you is fine

17:47 <sf-slack2> <nikolaus.luhrs> Ah yep, I see that now, I went ahead and joined the slack

19:10 <sf-slack2> <nikolaus.luhrs> I guess there's not really a getting started guide just yet?

19:33 <mithro> Someone poke me if I haven't pushed a new DB for prjxray in 3 hours - can you poke me again?

19:34 <mithro> Kergadon / nikolaus.luhrs: You might want to try and catch up with daveshah if you want to do ECP5 related stuff -- however I think a lot of ECP5 stuff is at the stage of "using the toolchain to do things" type area. There are a bunch of people doing cool stuff in the #litex channel like https://github.com/litex-hub/linux-on-litex-vexriscv

19:34 <tpb> Title: GitHub - litex-hub/linux-on-litex-vexriscv: Linux on LiteX-VexRiscv (at github.com)

21:35 <mithro> Latest database pushed! -> https://github.com/SymbiFlow/prjxray-db/commit/2e4d3dc3b2355c7b502ef778ff1ce8585e9d3889