<hackerfoo> ^ I think this is VPR's way of saying it can't route to an `.output` from the do of a slice l?
<hackerfoo> Maybe it's because I don't have enough inputs and outputs available in the new ROI.
<hackerfoo> No, this is before that, when generating the architecture.
<hackerfoo> I'm not sure what the SLICEL has to do with .output, then.
<hackerfoo> Maybe the error message is wrong?
<hackerfoo> Oh, there's a dummy design somewhere being run through VPR.
<hackerfoo> common/wire.eblif
<hackerfoo> I'm not sure why it fails, but it works if I remove the single input, output, and wire.
<hackerfoo> I guess I shouldn't be surprised that things are broken enough that VPR can't route from an input to an output, but I wish it gave some sort of hint as to why.
<mithro> hackerfoo: you can turn on verbose information on the clustering
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<hackerfoo> mithro: Thanks. I'll try setting --pack_verbosity higher.
<tpb> Title: vpr-20190729.txt · GitHub (at gist.github.com)
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<sf-slack2> <acomodi> mithro: filed the issue here, the current master+wip cannot be built in conda-packages until there is a fix: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/878
<tpb> Title: If Graphic packages are not installed VTR build fails · Issue #878 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)
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<litghost> hackerfoo: That error means that from the ".output" there is no pb_type routing from the blackbox to a tile pin
<litghost> hackerfoo: Actually try disabling the pin feasibility filter
<litghost> "FAILED Pin Feasibility Filter"
<litghost> We've had problems in the past where the pin feasiblity filter either was wrong, or prevent the diagnostic output that explained the failure
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<hackerfoo> > No possible routing path from cluster-external source (LB_SOURCE) to cluster-internal sink (LB_SINK accessible via architecture pins: outpad[0].outpad[0]): needed for net 'do' from net pin 'do.out[0]' to net pin 'out:do.outpad[0]'
<hackerfoo> I don't know where `out` is coming from.
<hackerfoo> Found this in testarch.echo: interconnect 2 OUTBUF.OUT outpad.outpad
<hackerfoo> <direct name="to_outpad" input="OUTBUF.OUT" output="outpad.outpad"/>
<hackerfoo> It's not from there, I renamed OUT to OUT_test and that didn't change anything.
<hackerfoo> Maybe it's because the model is blank for IOPAD.
<tpb> Title: symbiflow-arch-defs/iob33m.pb_type.xml at x1y0 · HackerFoo/symbiflow-arch-defs · GitHub (at github.com)
<hackerfoo> I want VPR to route IOB33M.O though OUTBUF to outpad.outpad, but I must be doing this wrong.
<hackerfoo> Can it route through pb_types?
<hackerfoo> Maybe I can put inpad/outpad inside INBUF/OUTBUF.
<hackerfoo> I can get a little further by connecting IOB33M.I/O directly to inpad.inpad/outpad.outpad
<hackerfoo> BTW this is the branch I've been working on: https://github.com/HackerFoo/symbiflow-arch-defs/tree/x1y0
<tpb> Title: GitHub - HackerFoo/symbiflow-arch-defs at x1y0 (at github.com)
<mithro> litghost: Did you see the following? [verilog-to-routing/vtr-verilog-to-routing] Add detailed timing report mode to VPR (#611)
<hackerfoo> Now I get this error:
<hackerfoo> There's no "switch" table in the database?
<hackerfoo> The database is empty.
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