18:57 <litghost> @mkurc: What is the state of yosys upstream master versus Symbiflow master+wip?

19:15 <sf-slack2> <mkurc> @litghost We have support for attributes on module parameters and port connections in our fork. There is a similar functionality regarding attrib. on parameters in upstream yosys but it differs in implementation. I am open to suggestions how to proceed further. I hardly believe that our features will end up in upstream.

19:16 <litghost> @mkurc: Is what is in upstream good enough? Can we change to use their implementation?

19:18 <sf-slack2> <mkurc> @litghost We are not using any of those features yet. They were ment for v2x. So I think we can use the upstream.

19:19 <litghost> @mkurc: Okay. Do you feel we should move master+wip back to master if that is the only difference?

19:22 <sf-slack2> <mkurc> @litghost I think that it is the only option. The upstream ver. has support for mocking module attributes as wires. We can make use of it in v2x in the future. So I see no obstacles.

20:05 <litghost> acomodi: Looks like we need to convert some VPR_THROW to VPR_ERROR: https://github.com/SymbiFlow/vtr-verilog-to-routing/pull/156/files#diff-92157f7cf1cca87f71dac8fa61f96a21R106

20:05 <tpb> Title: [pull] master from verilog-to-routing:master by pull · Pull Request #156 · SymbiFlow/vtr-verilog-to-routing · GitHub (at github.com)

23:23 <sf-slack2> <qinziyue.xu> Hi, I've tried to connect four buttons and four LEDs together on Arty, and two of the buttons are not working properly. From the history, it seems currently we do not support all buttons and LEDs. Can anyone confirm what we are supporting for Arty right now?

23:34 <litghost> qinziyue.xu: The harness for pin D9 and B8 seems wrong. Are those the two buttons you are seeing not work?