00:59 <hackerfoo> tmichalak: Do you have the source Migen used to generate https://github.com/SymbiFlow/prjxray/pull/1119? ZirconiumX in ##openfpga is interested in examples of how to use LiteDRAM.

00:59 <tpb> Title: minitests: Add test for Litex DRAM memory interface by tmichalak · Pull Request #1119 · SymbiFlow/prjxray · GitHub (at github.com)

01:10 <hackerfoo> Nevermind: https://github.com/antmicro/prjxray/tree/litex_litedram/minitests/litex

01:10 <tpb> Title: prjxray/minitests/litex at litex_litedram · antmicro/prjxray · GitHub (at github.com)

06:37 <owlhawk> I managed to run the fuzzers with Vivado 2018.1. Had to take out a part of 005-tilegrid related to the BSCANE2 block, which was causing a DRC error that I couldn't figure out an easy workaround for. No other issues though.

06:38 <owlhawk> mithro: I never encountered the issue #14 related to MUXF8 that you pointed me to last week

06:39 <owlhawk> Just started a run now with my first attempt at a spartan-7 configuration. Will see how that goes

06:43 <sf-slack> <tmichalak> Hackerfoo: Does nevermind mean that the minitest you found is enough or do you still neede the Migen source for it? I will be doing more Litex minitests and will add the target Migen sources there. In this particular minitest there is only final verilog.

06:44 <hackerfoo> It means I thought I found the source, but I think that's only for the full SoC.

06:45 <sf-slack> <tmichalak> Yeah, that's the full SoC

06:46 <hackerfoo> Do you have the source available? ZirconiumX was looking for an example of how to use LiteDRAM, and I thought the minitest might be a good one.

06:48 <sf-slack> <tmichalak> For the whole SoC? Let me have a look.

06:53 <hackerfoo> Wasn't there one for just the DDR controller? That's what I was looking for.

07:03 <sf-slack> <tmichalak> No, we don't have such a test yet. We really need to have it working with the vexriscv so we kept the SoC for now.

07:03 <hackerfoo> Okay, thanks.

08:41 <OmniMancer> what is the correct method to uninstall vivado on linux?

08:41 <sf-slack> <kgugala> OmniMancer: simply remove the directory where it is installed?

11:08 <sf-slack> <acomodi> @litghost: I cannot push force on yosys fork to update `master` and `master+wip` but I have created two `wip/` with the outstanding difference w.r.t to master, there is also a `new-master-wip` branch that includes the wip branches

11:09 <sf-slack> <acomodi> I think that we need an initial forced push to master+wip and than we can follow with the same strategy as for VtR with the integration points

12:36 <lromor[m]> Hi! I wanted to write some documentation. Is it possible to publish screenshots of the vivado view of the fpga schematics or it's not allowed by xilinx?

21:01 <_whitenotifier-e> [vtr-verilog-to-routing] litghost opened issue #333: Faster VPR rrgraph load - https://git.io/JeXwy

22:12 <bunnie> Are there any bits in the bitstream that are "unknownable", as in, no amount of fuzzing has revealed their function to date?

22:17 <bunnie> it looks like even the "undocumented" PHASER block is in the tilegrid, but is there a test or routine that checks for total bitstream coverage in case there are other blocks like that?