<promach>
I am trying to look at the signal "counter" in this module context
<promach>
but it is not available in the vcd
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<ZipCPU>
promach: Suppose you assign it via an initial statement.
<ZipCPU>
I'm going to assume that you haven't updated your yossys since the other day, so try not assigning your counter on the same statement as you declare it
<promach>
ZipCPU: already updated yosys 12 hours ago
<promach>
I sa that guthub commit
<promach>
saw*
<promach>
it is not really problem with assignment now, it is about the internal signal not shown in vcd file
<promach>
ZipCPU
<ZipCPU>
Just humor me.
<promach>
sure. I have removed the assignment od counter, still I could not see the counter signal in vcd
<promach>
assignment of*
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<ZipCPU>
If you place a (* keep *) in front of your declaration of counter, you'll force yosys to keep it.
<ZipCPU>
Your problem, however, is the $clog2 function.
<ZipCPU>
Your 8-bit value is getting 3-bits, which aren't enough to hold the value 8. Hence the counter is irrelevant, yosys is throwing it out, and the sampling_strobe is just plain set to 0.
<promach>
ZipCPU: I am really so careless and inexperienced in verilog coding :|
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<svenn>
that would not have happened with vhdl
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