clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZipCPU> promach: One of the challenges I have found with formal verification work is making sure that I constrain my design enough. In other words, you want to place as many asserts throughout your design as you can, or it will take forever to prove and be a pain to discover if it does (or doesn't) work.
<ZipCPU> So, I'll take a design that isn't proving as fast as I'd like, and I'll walk through the design adding assertions as necessary to keep it from every (accidentally) reaching an unused state in induction,
<ZipCPU> but also to make certain that I know as soon as possible if it ever hits an erroneous state during BMC.
<promach> ZipCPU: sure
<ZipCPU> Some of my projects now have more assertions than logic ... just so you know how much may be required.
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<promach> ZipCPU: ok
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