clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<mithro> Can anyone recommend a better simple way to get 8 LUTs cascaded together than ->
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<mithro> yosys / ABC seems to be optimizing away a bunch of my LUTs :-P
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<ZipCPU> mithro: Can you explain what you are trying to do?
<mithro> ZipCPU: Build a chain of 8 luts where the output of one lut goes into one of the inputs for the next lut
<ZipCPU> What's wrong with the code you posted?
<ZipCPU> Also ... did you see the response to the last post on reddit.com/r/FPGA? You might find it relevant to your question.
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