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<
daveshah >
I wonder if companies will change their mind once there is a full, practical bitstream flow for 7-series available....
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<
tpb >
Title: GitHub - djn3m0/debit: Reverse-engineering tools for FPGA bitstreams, Altera and Xilinx (at github.com)
15:54
<
daveshah >
It seems to still exist
15:57
<
sorear >
haven't found details on what "unfavorable attention" constitutes
15:57
<
daveshah >
The usual cease and desist notice, I would imagine
15:58
<
daveshah >
I find it hard to imagine what Altera would be able to claim though
15:58
<
sorear >
probably. I can't find any case files online for Altera and Jean-Baptiste Note or Éric Rannaud
15:58
<
daveshah >
I highly doubt it ever got to the point of an actual case, that would certainly be heavily publicised
15:59
<
daveshah >
Could have just been Altera threatening to remove the uni's freebies
15:59
<
sorear >
oh that's very likely
16:03
<
tpb >
Title: ALTERA CORPORATION v. CLEAR LOGIC INCORPORATED | FindLaw (at caselaw.findlaw.com)
16:07
<
awygle >
Depending on how the RE is done it could violate the terms of service
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<
philtor >
Yeah, I thought Xilinx was similarly agressive, yet we're able to generate some Xilinx7 bitstreams with yosys - what happened there?
16:26
<
awygle >
Small point of order, Yosys can synthesize to the Xilinx primitives but not create a bitstream. That's project x-ray (have they actually generated any bitstreams yet?)
16:27
<
philtor >
oh, I see.
16:27
<
philtor >
So you still need Vivado to go from those primitives (blif file?) to bitstream
16:27
<
daveshah >
I think bitstream generation is working. It's place and route that's missing - but is certainly being worked on
16:28
<
philtor >
how do you get to bitstream without p&r?
16:28
<
daveshah >
Manually
16:29
<
daveshah >
A language has been developed called "FPGA assembly"
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philtor >
link? Google not returning anything relevant for "fpga assembly"
16:32
<
tpb >
Title: FASM and xc7patch proof of concept using partial reconfig flow by kc8apf · Pull Request #55 · SymbiFlow/prjxray · GitHub (at github.com)
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<
tpb >
Title: prjxray/roi_noninv.fasm at b6f754dae7f4f9a2f073166c66f645d68b92ce3d · kc8apf/prjxray · GitHub (at github.com)
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<
kc8apf >
philtor: we've only documented CLBs and interconnect so far. We patch an existing bitstream that sets up IOBs, etc.
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ZipCPU >
philtor: Thank you for your encouraging comments.
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