clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<dmin7> hi, i wonder, has anyone ever done anything with icosoc raspi interface besides using it to write debug output? (reading data from it eg x)
<dmin7> or the SPI that is used for flashing from within C code ..
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<ZipCPU> Yes, dmin7, I've built the parallel port into a full bidirectional interface with a TCP/IP redirect
<dmin7> oh, nice .. is there some code i can look at?
<tpb> Title: GitHub - ZipCPU/icozip: A ZipCPU demonstration port for the icoboard (at github.com)
<ZipCPU> There's several parts to the interface. The FPGA side is kept in rtl/pport IIRC
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<ZipCPU> The pport->TCP/IP bounce takes place in sw/host/netpport
<ZipCPU> Programs using the interface would look something like the sw/host/wbregs program, and follow the interface in sw/host/devbus.h
<dmin7> i was affraid you were gonna say that (: .. i'm (still) using the picorv32/icosoc setup .. and as far as i can see your icozip doesn't have much to do with "icosoc"?
<xerpi> shouldn't typedefs be allowed outside of modules?
<xerpi> syntax error, unexpected TOK_TYPEDEF, expecting TOK_LOCALPARAM or TOK_ENDPACKAGE
<xerpi> I have a typedef inside a package and outside of a module
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<ZipCPU> dmin7: Ahh, I'm sorry, I missed that part of your question. :(
<ZipCPU> xerpi: In Verilog? Does yosys even support that?
<xerpi> ZipCPU, SystemVerilog
<ZipCPU> I didn't think yosys had full sV support (yet) ...
<xerpi> from the SystemVerilog standard "Types, nets, variables, tasks, functions, sequences, properties, and
<xerpi> checkers may be declared within a package. "
<xerpi> page 738
<xerpi> ZipCPU, yeah right
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<ZipCPU> Well .. the front end does recognize the token, so ... there's at least something there ...
<xerpi> I guess Verilog only allowed typedef inside of modules
<dmin7> ZipCPU: do you happen to have some instructions on howto get ICOZIP running (i'm using the icezero, not the icoboard, so i would have to adjust the pinout at least, i guess)
<ZipCPU> Sadly, no. I spent so much time getting the pport interface to work, that I never managed to get the CPU up and running.
<ZipCPU> Chief among the things to be done was the SRAM--I never managed to build the interface to it, or verify the code that uses that interface in simulation
<ZipCPU> The SPI might need some work as well, and then the software "demos"
<dmin7> oh, ok, i guess i'll just try to get some sort of SPI working between the pi and icosoc then
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<xerpi> is this a verilator bug or the standard?
<xerpi> bar1 and bar2 have different values
<xerpi> that's the full code: https://hastebin.com/raw/gayinosaju
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<ZipCPU> xerpi: Have you looked through the code Verilator creates??
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<mjo-uk_> s/our toosl/our tools/
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