clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<Exaeta> Hey ZipCPU I got an HX8K
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<Exaeta> can I write to a register while reading from it at the same time?
<Exaeta> would that be a data race in hardware? or would the register hold the output steady for a little bit until after the clock ends?
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<Exaeta> hum
<awygle> Exaeta: yes. "same time" isn't 100% accurate but the basic answer is yes.
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<Exaeta> awygle: so if I have unit A's data "read" from B and B's data written to C in a clock cycle, C wont end up with the data in A right?
<Exaeta> awygle: not really sure what part you meant yes to
<awygle> not really sure what your question is. if you have registers A, B, and C, where A=1, B=0, C=1, and on each clock cycle you store A into B, B into C, and C into A, then next clock cycle you'll have A=1, B=1, C=0
<sorear> not sure I understand your question either, but verilog "reg"isters are ideal flops with zero setup and hold time, the synthesis tools will ensure that setup and hold requirements are met
<sorear> a register can be almost anything that holds a value at several different levels of abstraction
<Exaeta> ok, well I'm basically trying to write an array of "stack register"s, which when they receive the push or pop signal, will copy data up or down the stack
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<promach> awygle: I saw that you did not use "mode prove" as in http://symbiyosys.readthedocs.io/en/latest/quickstart.html#beyond-bounded-model-checks
<promach> but I could be wrong
<promach> I need time to look at your https://github.com/awygle/spirit/blob/uart_lite_wip/uart_lite/verification/character_recovery_formal.v , I might need to follow in your footstep. I am stucked at UART formal verification for far too long :(
<promach> awygle: you are using "mode cover" instead ?
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<jkiv> Not sure if this is the right place to ask, but are ICE40 chips able to be flashed in parallel (N chips at once) in SPI slave mode?
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<Exaeta> what's the general workflow for making verilog code?
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<Exaeta> say I want to write code from scratch and compile it from the command line
<jkiv> Exaeta, w.r.t. your messages earlier (as I read the chat logs), that was me with the HX8K development board.
<Exaeta> jkiv: oh okay
<Exaeta> ZipCPU: which FPGA were you able to make a working CPU on?
<Exaeta> jkiv: does the uart example work for you?
<Exaeta> it doesn't seem to do anything for me
<jkiv> Exaeta, not sure, I dove straight into my project when I got mine, lol
<jkiv> Exaeta, is it available on github?
<Exaeta> yeah
<jkiv> Exaeta, looks like it's targeting the 1k
<jkiv> but it appears to be a nice little state machine example.
<awygle> promach: I did both prove and cover at a depth of 200
<Exaeta> jkiv: oh, weird
<Exaeta> the blinky thing only compiled for the 8k
<Exaeta> by default
<Exaeta> so I thought all the examples were for the 8k :/
<jkiv> Exaeta, yeah the main README suggests that as well: "ICE40 HX8K Example Projects"
<Exaeta> oh yeah it worked on my 1k
<Exaeta> interesting
<jkiv> Exaeta, I don't think they're official examples
<jkiv> :S
<jkiv> But yeah, the pinouts and make parameters are going to be device-specific :/
<Exaeta> just out of curiosity, could I hook up multiple devices together with the GPIO pins? and create a shared data bus
<sorear> sure. it may not be as fast as you like
<Exaeta> how fast does GPIO switch?
<Exaeta> like what data rate can I expect per bit I dedicate to I/O?
<sorear> it would say in the chip documentation
<Exaeta> 250 MHz I/O output, but doesn't say how many bits per cycle
<sorear> 1
<sorear> per pin
<Exaeta> actually it doesn't say that, it says that for a specific protocol it can run at that frequency in the worst case... I don't think it applies in general to the I/O pins themselves
<Exaeta> is there a keyword in specific I'm looking for to find the I/O rate on the pins?
<jkiv> Exaeta, not exactly sure myself, but probably "iCE40 External Switching Characteristics – HX Devices" in the ICE40 Family Handbook
<sorear> Exaeta: i'm looking at "Maximum sysIO Buffer Performance"
<Exaeta> I guess I'm looking at Pin-LUT-Pin Propagation Delay for the maximum performance here?
<Exaeta> hum
<Exaeta> seems the pins are not buffered or switched or anything
<Exaeta> they can be connected directly to gates
<Exaeta> I think
<Exaeta> so... roughly 100Mhz per pin, I think?
<Exaeta> 100Mbps per data pin, I guess
<Exaeta> so, roughly 20Gbps max if all 200 pins are used for i/o... ignoring the time to do buffering and synchronization calculations
<Exaeta> that seems... fast enough
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<Exaeta> Are there any ICE cards that can be plugged into a PCIe slot, for example
<Exaeta> i.e. anything faster than usb?
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<ZipCPU|Laptop> Exaeta: Exaeta-mobile: While I have an Hx8K board, that's not the one I have. I've got an icoboard. See icoboard.org (IIRC)
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<Exaeta> ZipCPU: how did you manage to get a CPU in this few gates?
<Exaeta> I saw the example tile viewer thing...
<Exaeta> a single adder took up like 3 tiles
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<ZipCPU|Laptop> Exaeta: Did I manage to get a CPU in this few gates? Of course! I think I fit in about 4k of them.
<ZipCPU|Laptop> There was another individual who managed to get a CPU to fit in 1k gates, but as I recall it was a very simple forth based CPU running off of 8'b instructions
<sorear> how many peripherals do you need before it counts?
<ZipCPU|Laptop> :D
<ZipCPU|Laptop> That's a really key question.
<ZipCPU|Laptop> For me, I need a means of debugging the CPU (which wasn't present in the 1K example), and some block RAM.
<ZipCPU|Laptop> An internal timer makes it possible to run multiple tasks.
<ZipCPU|Laptop> Accessing the boards off-chip RAM (if it has any) is also key.
<ZipCPU|Laptop> But ... I'd count a CPU even if it didn't do that.
<sorear> how does debugging usually work with softcores? how do you usually go about routing the debug signals from the core to the board tether?
* sorear needs to actually study JTAG at some point
<ZipCPU|Laptop> sorear: I'm not sure I can speak to all soft-core CPU's. I think OpenRISC is using an open JTAG suite for debugging, but that requires some GPIO pins to be repurposed for JTAG
<ZipCPU|Laptop> I use an 8-bit channel of some type, and apply some coding over the channel so it will carry WB bus operations. I call this a deugging bus. The CPU is then accessed as a slave off of that bus, and an arbiter decides whether the CPU or the debugging bus gets access to the rest of the bus.
<ZipCPU|Laptop> For the 8'bit channel, I've used JTAG USER instructions on a Spartan FPGA--very similar to a SPI port, and I've used a parallel port from the RPi, but most often I just use a serial port for that purpose.
<ZipCPU|Laptop> Much to my surprise, although it really made perfect sense in hindsight, I have some complex debugging bus implementations that ... just won't fit on the iCE40 8k part.
<sorear> It seems problematic if you need separate JTAG headers, etc for the FPGA itself and for the custom logic. I'll have to look into USER
<ZipCPU|Laptop> Agreed, that was my view of things as well.
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<sorear> hmm, I've found 1149.1:2001 but not 1149.1:2013, hope it hasn't changed too much
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<sorear> why does this document use 1 with an overbar instead of 0
<sorear> so JTAG requres TDO to be 'z in certain states. is that requirement typically ignored on fgpas?
<sorear> logic symbols I've never seen before in this doc :x
<cr1901_modern> I only know jtag to the extent that I can program an fpga/write a bitbang program to read out the id
<cr1901_modern> Its served me fine so far
<cr1901_modern> Though I should prob learn how to use JTAG for debugging
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<sorear> having now read the jtag (aka TAP, Boundary Scan) and risc-v debug specs, this is simpler than I feared but not quite trivial
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<sorear> 4 bits JTAG state, 2 bits selected instruction (IDCODE/BYPASS/DTMCS/DMI), 39 bits JTAG DR/IR shift register, 1 bit dtmcs sticky error, 1 bit(maybe more if we need to expose partial states?) halt status, 2 bits (unclear) dmcontrol reset state, 32 bits data0, 32 bits progbuf0, 2 bit abstract command error, 6 bits (mandatory fields in dcsr) = 121 bits new state
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<Exaeta> ZipCPU: I would think that you'd run out of gates pretty quickly. Given how many a single reg takes up.
<Exaeta> My ideas for a pipelining cpu are smashed. :P
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<Exaeta> at least I don't think I can do it on this fpga... too small
<Exaeta> I think I'm also gonna need to drop the register count too
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<ravenexp> registers are very cheap on fpgas
<ravenexp> cpu registers, I meant
<ravenexp> 32 GPregs or 128 GPregs won't make much difference
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<Exaeta> my understanding is that it would be difficult to implement pipeline and cache with such a small number of gates
<Exaeta> or multiple cores
<ravenexp> the FPGA isn't a sea of gates
<ravenexp> when designing for FPGAs, you have to exploit its structure
<ravenexp> as an example, FPGAs have very efficient small SRAM blocks
<ravenexp> they are always there, and if your design doesn't make use of them they are wasted anyway
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<ravenexp> same goes for hardware multipliers/MACs
<Exaeta> ravenexp: what's the memory latency in cycles?
<Exaeta> but multiplication is just a bunch of shifts and adds. :L
<ravenexp> typically 1 cycle for big blocks, can be made async for very small sizes
<ravenexp> wide multipliers are huge in chip real estate terms
<ravenexp> that's why most fpgas have them as hardened macros
<Exaeta> You can do it in like O(N log N) gates
<ravenexp> FPGAs don't have user programmable gates
<Exaeta> with O(log N) stages.
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<Exaeta> yeah they have lookup tables? :s
<ravenexp> try to build a single cycle 32x32 multiplier out of 4-LUTs and you'll see
<Exaeta> it seems a bit weird to me
<Exaeta> are there any FPGA that are effectively a "sea of gates"?
<daveshah> no large ones
<daveshah> it's only small CPLDs that use that approach AFAIK
<daveshah> I think there is some research into sea of gates FPGAs, but nothing commercially available
<ravenexp> aren't small CPLDs basically IO->logic->FF->IO structured?
<ravenexp> with even less real flexibility that big fpgas?
<Exaeta> Is this just a result of density issues?
<ravenexp> gates are small and fast, wires are huge and slow
<Exaeta> hummm
<ravenexp> user programmability reuires lots and lots of wires
<Exaeta> and a 4 bit lut is the most efficient way to implement it?
<daveshah> most modern fpgas use larger luts
<daveshah> 6 or 8 input
<daveshah> often with cascade logic too
<ravenexp> xilinx uses 5/6 input LUTs
<ravenexp> the ones you can buy, that it
<Exaeta> So my idea of an array of stack registers that shift data up and down might not be efficiently implementable on a FPGA?
<daveshah> in the ultrascale they also have muxes to combine 4 6-luts into an 8-lut, or 8 6-luts into a 9-lut
<Exaeta> better to just use sram?
<daveshah> yes, I'd say so
<Exaeta> Is main memory of the FPGA all sram?
<ravenexp> there are flash-based fpgas
<ravenexp> but they lag behind in capacity
<Exaeta> So I guess a CPU on an FPGA wouldn't have any cache?
<ravenexp> you can use SRAM blocks for cache
<ravenexp> there are aplenty
<Exaeta> ... but what's the point if that's the only type of memory you have
<ravenexp> to use external DRAM?
<Exaeta> I don't think ICE40 supports that, does it?
<ravenexp> ICE40 isn't the only thing out there
<ravenexp> and you can attach an external sram chip to it
<Exaeta> Isn't it the only thing programmable with open source tools?
<ravenexp> there was even a eval board like that
<ravenexp> OSS-programmable FPGAs are an exception
<Exaeta> I bought the HX8K because it was the fastest FPGA with an open source toolchain, or so I thought.
<Exaeta> I guess something needs to be reverse engineered here. :/
<ravenexp> if xilinx made iCE40, it'd call it a CPLD :)
<ravenexp> it's that small
<Exaeta> ravenexp: What do you mean?
<ravenexp> iCE40 targets the very low end of the market
<ravenexp> like replacing the fixed function logic
<Exaeta> Will intel refuse to release documentation for the bitstream of its devices?
<ravenexp> you meant altera?
<Exaeta> that
<ravenexp> I think its very unlikely
<Exaeta> Why would they refuse to release information about the protocol?
<ravenexp> you say "refuse" as if they are somehow obligated to do it
<Exaeta> I mean, if you sell a product
<ravenexp> nobody releases such specs
<Exaeta> it's implied warranty of fitness for a particular purpose
<ravenexp> what
<ravenexp> you just pay some 4 figures for the the vendor software license and you are good to go
<Exaeta> If I sell you a "smart washing machine" but it contains no software, that's a violation of the implied warranty of fitness for a particular purpose.
<ravenexp> that's how the stuff has been working for decades
<Exaeta> yeah, probably not legal.
<Exaeta> ianal, but I do study this subject in my spare time
<Exaeta> I think it would also be considered copyright abuse.
<Exaeta> Since the right to use the device transfers under the "first sale" doctrine.
<ravenexp> welcome to the world of fpgas: full of erratas, outrageous prices and buggy vendor software with restrictive licensing
<Exaeta> My dad's next-door neighbor is a high-end IP lawyer, maybe I'll run it by him and see what he thinks.
<ravenexp> Exaeta: have you ever bought a GPU?
<Exaeta> yes
<Exaeta> probably also a violation, technically.
<ravenexp> if something is violated as a rule, then maybe it shouldn't be called a law?
<Exaeta> Well, the speed limit is still the law even though everyone breaks it.
<Exaeta> And you can still be ticketed
<Exaeta> (although usually you can go about 5 over because police don't want to be in court testifying about the calibration of their radar)
<Exaeta> Of course, some judges are very corrupt, and might just ignore the law and decide that the corporations should win just because
<Exaeta> that's probably what these tech companies are relying upon
<Exaeta> The federal circuit, is unfortunately, one of the worst offenders here.
<Exaeta> though it might be more incompetence than corruption
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