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<jwhitmore>
I'm probably reading the wrong document to start with http://www.clifford.at/yosys/files/yosys_manual.pdf I'm only starting out with a TinyFPGA and hoped to possibly flash an LED or something.
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<jwhitmore>
I've an embedded SW background so if this was a new uC I'd be looking at the datasheet for the part. And finding the registers that drive the pin I wanted
<jwhitmore>
This ain't that. So possibly need the idiot's guide. Any suggestions would be very gratefully received.
<awygle>
* synthesize it in Yosys with the synth_ice40 command
<awygle>
* place and route it with arachne-pnr
<awygle>
* program the resulting bitstream file onto your board in a variety of ways
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<awygle>
(* it doesn't work, profanity, hair-pulling, debugging, eventual understanding)
<awygle>
For general FPGA development, ZipCPU has an excellent blog - http://zipcpu.com/
<awygle>
If you have specific questions feel free to ask here or in ##fpga and somebody will be able to help
<jwhitmore>
awygle, Deadly thanks for all of that! That's the one thing I did pick up from the yosys manual was that I'm going to have to find out about Verilog language
<ravenexp>
btw, is it possible to generate invalid bitstreams with arachne-pnr?
<ravenexp>
like attaching multiple drivers to the same wire
<daveshah>
ravenexp: No, it won't let you do that
<ravenexp>
or making a ring oscillator on a string of LUTs
<awygle>
ravenexp: it shouldn't be - if such was allowed that would be a bug
<daveshah>
ravenxp: Ring oscillators are fine and work
<ravenexp>
I was wondering if it's possible to damage the silicon with bad configurations
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<awygle>
ravenexp: I suspect you could craft a bitstream to do that outside arachne. I don't know of anyone doing so on an ice40 but it's been done on a Coolrunner II
<ravenexp>
oh, cool!
<jwhitmore>
awygle, I'm sure that'll be a good enough place to start and from there I'll at least have sensible questions.
<awygle>
jwhitmore: cheers, welcome aboard!
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<ravenexp>
google has failed me, where can I read about that bad coolrunner bitstream thing?
<sorear>
how robust are 7-series parts against that kind of thing?
<sorear>
even if you completely trust the toolchain, you still have to worry about cosmic rays flipping configuration bits in the device itself
<awygle>
ravenexp: azonenberg is the one who did it, here's something from Twitter...
<sorear>
it's nice if those are only SEUs and not damage events
<awygle>
sorear: an excellent question, possibly answerable with the SymbiFlow docs. at the very least I'd expect some ecc scrubbing to fix configuration mistakes
<sorear>
presumably the internal prep work for F1 included a full evaluation of "can people fry the chips with bad partial reconfig", and it was ruled out as a possibility
<ravenexp>
xilinx can do bitstream CRC scrubs
<awygle>
(now that everything we build is built on quicksand I assume everything assumes any bit can change at any time)
<awygle>
sorear: maybe ask Jan Gray about that?
<awygle>
I could see them saying "eh vivado won't do that"
<ZipCPU>
If you do a "make bin" in the rtl/ directory, it *should* (it's still a work in progress) build an iCE40 design that *should* work on the TinyFPGA--I just haven't fully fleshed out the design or passed simulation with it yet.
<awygle>
ZipCPU: if you ever find yourself with a surplus of time (ha), we really need a decent Verilog tutorial
<ZipCPU>
Sigh. Yes. So true.
<ZipCPU>
Folks have also asked me about what would constitute a good text book to start from as well.
<ZipCPU>
I'm not sure I've seen one, since learning Verilog really needs to start with how you debug Verilog designs and most text books seem to ignore that fundamentally valuable piece of coding.
<awygle>
It's very chicken-and-egg
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