<awygle>
promach_: yes, center sampling, sometimes with some amount of voting
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<promach_>
voting ?
<promach_>
I am now stucked at induction check involving parity error
<promach_>
awygle: what do you mean by "some amount of voting"
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<awygle>
promach_: sometimes instead of sampling once at the center of the bit, you sample three times centered at the center of the bit, and take the majority
<awygle>
it's for glitch rejection
<awygle>
and obviously that doesn't need to be 3 times, it could be 5 times, or 7 times
<awygle>
i did not. what i did there was require the bit to be constant for an entire bit duration or be rejected
<awygle>
which is overly conservative
<promach_>
not over conservative, but good for noisy physical environment
<promach_>
where do you implement the voting ?
<promach_>
awygle: votng is your TODO , am I right ?
<awygle>
promach_: correct
<promach_>
awygle: your UART Rx coding looks minimal which is good for logic resource from first look.
<awygle>
promach_: that's the idea ("lite"). i want it to support most UART features, but at compile time by parameters, not at runtime by configuration registers
<promach_>
I see, but how do you detect start bit ?
<awygle>
in charater_recovery, i leave IDLE on a rising edge
<awygle>
i originally had an edge detection module but realized it was too trivial to bother separating
<promach_>
wait, what are 'valid_i' and 'valid_o' ?
<awygle>
promach_: "valid_i" is "a bit is valid". "valid_o" is "a character is valid"
<awygle>
"valid_i" will go away when i fold bit_recovery into character_recovery.
<promach_>
I am not quite sure about the purpose of having "counter != {COUNTSIZE{1'b0}}"
<awygle>
promach_: i found that through formal verification, actually. that's needed because otherwise i won't register back-to-back bits of different values correctly. they'll have to be 17 samples wide instead of 16 samples.
<awygle>
that's basically saying "the value is allowed to change between bits"
<awygle>
which is it
<awygle>
*which it is
<promach_>
register back-to-back bits of different values correctly ??
<awygle>
okay so the start bit is a 1, which means rx_i is high for 16 cycles. on the 16th of those cycles, counter is 15, hold is 1, rx_i is 1. right?
<awygle>
if the next bit is a 0, rx_i becomes 0. counter is also zero, and we want it to "count" this sample and increment to 1. but hold is 1, so hold != rx_i. if we didn't have counter != {COUNTSIZE{1'b0}} in the condition, we'd re-set counter back to 0, so it would count 15, 0, 0, 1, 2, 3 instead of 15, 0, 1, 2, 3.
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<promach_>
awygle: I see. Why do you need to implement voting when you already had a good, conservative bit_recovery.v ?
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<awygle>
promach_: i find my current implementation to be overly conservative. the main problem is that it only allows a 0.625% difference between bit clocks (at an oversample of 16)
<promach_>
I see, rise and fall time of a bit does not allow overly-conservative bit_recovery.v
<awygle>
in 8N1, a character is 10 bits total, and my current implementation means you're not allowed to slip _any_ clock cycles, so you're allowed a change of less than 1/16th of a bit over 10 bit = 1/160 = 0.00625
<awygle>
if sampling at the center, you're allowed to slip up to 8 clock cycles, so 8/160 = 5%
<awygle>
same if doing 3-bit voting (because the majority vote will wash out the last incorrect sample)
<promach_>
why use oversampling factor while you could sample using the system clock which is way faster?
<Exaeta>
awygle: I assume if I mess up and write multiple 1s to the same wire it'll multiple the current/voltage and fry things?
<awygle>
Exaeta: actually writing a 1 and a 0 is the dangerous thing. it becomes a short from power to ground. but yes, if you do the wrong thing with multiple drivers it will melt your chip.
<promach_>
awygle: what I mean is using sampling clock with period of "1/(clk frequency)"
<promach_>
it does not matter what baud rate you use
<awygle>
promach_: i understand. but then the UART core needs to know the baud rate and the system clock rate in order to calculate how to delay by "half a bit". this way all the UART core needs to know is the oversampling factor.
<promach_>
that is the advantage of run-time compilation which is your long term design goal, I suppose ?
<promach_>
cut out the run-time from my previous comment
<promach_>
which would do you the logic saving if you are concerned about logic usage
<promach_>
sampling using a faster clock would also be a good thing as well
<awygle>
well, not necessarily. faster clocks mean more power. but it does give finer resolution to your glitch rejection and whatnot.
<Exaeta>
awygle hum. I thought that a 0 was just "no current"
<awygle>
it's probably a good idea just for simplicity of not crossing clock domains if i switch to a CE signal though. i might do that later. i am exploring the design space as i write the code.
<awygle>
Exaeta: no, a 0 is "no voltage relative to some reference point which we call ground"
<promach_>
you already have a faster system clock compared to your "oversampled" clock
<promach_>
awygle: this faster clock is actually your system clock
<promach_>
you are not using the system clock to your advantage
<awygle>
promach_: you're correct. there are tradeoffs to doing it your way but i think i'm coming around to your point of view.
<promach_>
you could also save a few logic on count as well if you use system clock
<awygle>
and avoid a clock domain crossing
<awygle>
well i'm leaving work now, ater dinner i'll put some more work into it.
<promach_>
I am not sure about CDC when using "oversampled" clock
<promach_>
because it is also done within the realm of the system clock
<promach_>
I also got to go
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<Exaeta>
awygle: so, if I had diodes on each output, would that work?
<Exaeta>
or no
<awygle>
Yes, a diode OR is common
<awygle>
Also "open drain" or "open collector"
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<awygle>
i had looked at UVM before but mostly ignored SystemC, but someone on reddit pointed out the (obvious in hindsight) synergy with Verilator
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<awygle>
excellent! back to passing all my assertions and cover statements
<awygle>
still not entirely comfortable with the kind of garbage waveforms that are accepted as valid data now, but i suppose "i am hooked up to something resembling a UART" is a decent operating condition to require
<awygle>
promach: i pushed my new stuff to github, feel free to take a look
<promach>
promach: let me have a peek. I am curious how you designed your cover() statement
<promach>
mine one still had not passed induction :(
<awygle>
although i still want to add polarity inversion and parity support
<promach>
awygle: are you still using overly-conservative bit check that you told me about few hours ago ?
<awygle>
promach: no, this version is doing a single sample at the center of the bit
<awygle>
it would be easy to go back to the other solution if desired. but none of the UARTs i found online worried about "adversarial" data
<promach>
I saw it. Line 51 :)
<promach>
awygle: your Rx code structure looks simple. I love it
<awygle>
promach: glad you like it :) it may not be the most efficient, i intend to take a look at what yosys synthesizes and possibly improve it, but for learning i like this style.
<promach>
awygle: did you forget your 2FF synchronizer pair ? or did I miss it in the code ?
<awygle>
promach: i didn't put that in yet. i am planning to put it in a larger wrapper that will also include the TX section and possibly a deglitch circuit
<promach>
deglitch circuit ? could you tell me more ?
<awygle>
promach: i try to keep modules to one clock domain
<promach>
what is the deglitch circuit for ?
<awygle>
promach: a deglitch circuit would just take in a duration (in terms of system clock periods) and suppress any pulses that are shorter than that duration. so if the input is high, then goes low for two clock cycles, then goes high again, a three-cycle deglitch would cause the output to remain high.
<awygle>
i am going back and forth on including it. many UARTs in microcontrollers have a configurable deglitch, but i sort of feel that i shouldn't be making my core any more permissive than it already is...
<promach>
ok, I see
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<awygle>
promach: i'm getting ready to go to sleep, are there any questions i can answer before i go? does the verification element make sense?
<promach>
awygle: go and have some quality rest
<promach>
I need some time to look at your cover() statements
<awygle>
will do :-)
<awygle>
ZipCPU: I'd love your input as well if you have time to take a look tomorrow
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<promach>
awygle: just a side note, if you are designing for ASIC, you probably need 'RESET' signalling mechanism for UART. I am not an ASIC guy, I could be wrong
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<ZipCPU|Laptop>
awygle: I'm not at my desk this week, so I'm not sure I can promise much.
<ZipCPU|Laptop>
However, I was working on my own UART implementation the other day ...
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<shapr>
Exaeta: Xilinx sells twelve thousand dollar FPGAs that have 64GB of memory, 2.8 million logic gates, and everything else you might want (Virtex UltraScale+ XCVU37P)
<sorear>
the chip you have is $9 in bulk
<Exaeta>
ah. that makes more sense
<Exaeta>
1000x logic gates, 1000x price
<shapr>
Exaeta: are you getting into FPGAs for school or fun or what?
<Exaeta>
self education I guess
<Exaeta>
my school sucks
<Exaeta>
and/or just fun I suppose
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<Exaeta>
looks like this board works on the examples without modification
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<Exaeta>
the UART demo isn't working though
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<kc8apf>
Exaeta: what board?
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<shapr>
Exaeta: did you get the hx8k dev board?
<shapr>
self education is a good reason, same reason I got the hx8k board
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<Exaeta-mobile>
shaprL I got ct256 or something like that I think
<Exaeta-mobile>
shapr*
<Exaeta-mobile>
I don't know if it's a "dev board" or not though