clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach_> ZipCPU: https://gist.github.com/anonymous/99dfccd066baad6d441bbf4a105a2974#file-test_uart-v-L146 failed, so I am trying to see the genvar variable 'Tx_shift_reg_index' waveform in gtkwave
<ZipCPU|Laptop> Ahh ... okay, there's an easier way to do that.
<ZipCPU|Laptop> Create an array, where each of the values within the array will be the inside of the assert statement.
<ZipCPU|Laptop> The assert(array_name[Tx_shift_reg_index]);
<ZipCPU|Laptop> The array will show up within the trace file.
<ZipCPU|Laptop> The array element that is false will indicate which part/piece had the problem.
<promach_> ZipCPU|Laptop : so, use array instead of genvar ?
<ZipCPU|Laptop> No, you can still use the genvar to set the array values.
<promach_> I do not get what you mean
<ZipCPU|Laptop> wire [INPUT_DATA_WIDTH-1:0] arrayname;
<promach_> use genvar to set the array values ?
<ZipCPU|Laptop> Within your design, change if (A)&&(B)&&(C) assert(V[k]==D[k]) to ...
<ZipCPU|Laptop> assign arrayname[K] = (!A)||(!B)||(!C)||(V[k]==D[k]);
<ZipCPU|Laptop> Then, still in the same for begin-end block, assert(arrayname[K]);
<ZipCPU|Laptop> Just make certain that arrayname is defined outside of the generate block.
<ZipCPU|Laptop> s/Within your design/Within your generate for statement/
<promach_> ok, predicate logic simplication trick ?
<ZipCPU|Laptop> The only simplification is changing (AB)->C to (!A)||(!B)||(C)
<ZipCPU|Laptop> Within my own logic, I just wrote all 8 of the checks out.
<promach_> I see
<promach_> let me try your suggestion later. I need to go now. I shall come back to this in an hour or two
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<promach> ZipCPU , ZipCPU|Laptop : changing (AB)->C to (!A)||(!B)||(C) I do not understand the second logical OR operator
<ZipCPU|Laptop> !(AB) = (!A)||(!B), right?
<promach> I suppose we should use logical AND operator instead ?
<promach> no mean for C
<promach> no, I mean for C
<ZipCPU|Laptop> if(A) then (C) is only ever false if (A) and (!C) are true.
<ZipCPU|Laptop> Hence, you can replace if (A) then (C) with (!A)||(C)
<ZipCPU|Laptop> Hence, an expression like if (PIGS_FLY) then (POLITICIANS_ARE_HONEST) will be trivially true for all politicians.
<promach> ok
<cr1901_modern> Hah.
* cr1901_modern is amused but can't muster up a better response tonight- ENOENERGY
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<Exaeta> Hello. I want to develop for FPGA on linux. What FPGA should I buy for under $400?
<ZipCPU> Exaeta has a question for all of you ice40 types: what's a good beginners ice40
<ZipCPU> I suggested an 8k part of some type.
<ZipCPU> I have an icoBoard, a blackICE board, and a TinyFPGA board. I'm hesitant to recommend any of these because I'm not sure how mainstream they are.
<Exaeta> Where do you buy these btw? Amazon doesn't have a large selection
<ZipCPU> Check out Trenz Electronics for some of these.
<ZipCPU> But ... I thought there was a pretty good Ice Stick eval board, and I'm hoping someone else on the channel can remind me of what it was.
<Exaeta> I'm curious what's the most powerful FPGA that works with yosys/open source
<Exaeta> I want to make a 16-bit cpu
<ZipCPU> Then you'll definitely want the 8k part.
<ZipCPU> While you can build a CPU in the 1k part, you'll find yourself very limited.
<ZipCPU> I've managed to fit the ZipCPU on the 8k part tho.
<ZipCPU> (ZipCPU is a 32-bit CPU, with two sets of 16 32-bit registers)
<Exaeta> ZipCPU: so you made your own CPU? how fast is it compared to intel cpus?
<ZipCPU> Lol!
<Exaeta> slow? haha
<ZipCPU> FPGA's don't run as fast as custom designed chips. I think the rule of thumb is that there's an order of magnitude speed difference between the two.
<ZipCPU> The fastest I've run the ZipCPU is about 100MHz.
<ZipCPU> I built one design for 150MHz or so (I was pushing for 200), but the project stopped when the peripherals wouldn't support the speed I wanted.
<Exaeta> ZipCPU: so a minimum of 10x slower excluding instruction set advantages?
<ZipCPU> Well, yeah but ...
<Exaeta> or like 100x? humm
<ZipCPU> You can "buy" speed with FPGA logic.
<Exaeta> why are FPGA so much slower?
<ZipCPU> So you might find that a bigger FPGA is faster than a smaller one.
<ZipCPU> So the comparison is between "FPGA"s and "ASIC"s.
<ZipCPU> FPGA's are slower than ASICs because they have to be so general purpose.
<awygle> Exaeta: i'm guessing you ended up here through learning about the icestorm project, but is an open source toolchain actually important to you? or do you just want to devleop for FPGAs on Linux?
<Exaeta> awygle: I mean, I prefer open source. but I guess it depends on the performance differences
<sorear> the logic elements in an FPGA are much further apart, which makes your timing worse by about a factor of 10; i'd be curious to know more about how sram and flash fpgas compare to ASICs in terms of energy per operation
<jkiv> I started with the Lattice ice40hx8k development board and it's been pretty good.
<sorear> i assume "much worse" but I couldn't guess if 10x or 1000x
<ZipCPU> jkiv: What's that board called?
<jkiv> "ICE40HX8K-B-EVN"
<awygle> Exaeta: so the ice40 HX8K is the biggest part fully supported by open source tools, and the https://www.olimex.com/Products/FPGA/iCE40/iCE40HX8K-EVB/open-source-hardware is pretty well recommended (though i do not own it)
<jkiv> lattice branded
<Exaeta> awygle: got any supplies in the USA?
<Exaeta> *suppliers
<jkiv> awgle: that's the one! programmable over USB. I'm running windows and I'm able to program it from a Linux virtualbox instance
<Exaeta> awygle: what kind of cable do I need?
<jkiv> awgle*
* jkiv is tired apparently
<Exaeta> it says usb but doesn't specify usb mini, type A, etc
<awygle> in terms of "what are the performance differences"... the ice40s are very small, very low power FPGAs. for comparable cost you can get many times the number of logic elements. for instance https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/ is about 4x the elements, while the https://hackaday.io/project/13048-flea-ohm-fpga-project/details is 3x (in the Ohm+ variant)
<awygle> but again, no open source toolchain
<awygle> so it's up to you
<awygle> Exaeta: usb mini-b
<jkiv> Exaeta, it came with a cable. It's the larger mini type
* ZipCPU is quite tired. If he issues a WAIT instruction, he'll switch to SLEEP mode until the morning alarm INTERRUPT.
* awygle claims awgle as his own
<Exaeta> 4x isn't that bad
<Exaeta> I think I'll stick with the open source version
<awygle> sounds good :)
<Exaeta> another question
<Exaeta> can I write the program to an FPGA where it will store it in memory?
<Exaeta> or does it always need to be connected to the computer?
<ZipCPU> Exaeta: I think you have your terms confused.
<ZipCPU> FPGA's don't run programs, CPU's do.
<awygle> most FPGAs are SRAM-based and lose their configuration when power is removed. they can be loaded over JTAG (which is what you do with the usb connector), or they can read it from a discrete Flash chip on the board (which can also be programmed over the same JTAG link, in most cases). i'm not sure if the Lattice board has a flash chip but i'd expect it does
<ZipCPU> An FPGA developer will create a "design", which can then be loaded into an onboard "configuration"
<awygle> update: it does have such a flash chip.
<Exaeta> Can I write to the flash chip with open source tools?
<ZipCPU> I certainly do.
<awygle> good question. i'm going to say "probably"
<jkiv> Exaeta, the board I mentioned earlier does both -- can store your config, or require reprogramming on power cycle
<awygle> ZipCPU knows better than me lol
<ZipCPU> Whether or not the tools I work with would work for your board, I wouldn't know.
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<sorear> the lattice and xilinx fpga chips always require reconfiguration after a power cycle. sometimes they can do it automatically.
<awygle> sorear: well, lattice does have some (XO2) with internal nonvolatile storage
<awygle> they barely count as fpgas though
<sorear> in what sense do they barely count
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<awygle> actually, i rescind that. i remembered them as having hundreds of LUTs and being more like CPLDs, but apparently i was wrong.
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<sorear> what's the dividing line between cpld and fpga
<awygle> a question of some debate, but the best explanation i've found is that FPGAs are based on LUTs+FFs and a routing fabric while CPLDs are based on product terms. rqou explained it better at one point.
<awygle> *product terms and a crossbar
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<Exaeta> ok so... I need to do... something... uh
<Exaeta> which should I get?
<Exaeta> lol
<jkiv> Exaeta, what's up?
<jkiv> haha
<Exaeta> I want one that keeps config
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<Exaeta> without having to have an attached cpu
<Exaeta> so I can make like, a mini cpu thing
<Exaeta> (wouldn't be very useful if it had to be connected to a PC as well)
<Exaeta> I hope this works
<Exaeta> Also anyone know how to deal with this? https://pastebin.com/szmMdjL6
<sorear> most SRAM FPGAs support being connected to a flash chip so that they automatically configure themselves from the flash chip on power-on with no other support needed
<Exaeta> I think it's because I had to edit the makefile?
<Exaeta> I only changed it to clang-3.8 and clang++-3.8 and from -Os to -O2 though
<ZipCPU> Sigh ... you did what? Tell me in the morning ...
<jkiv> Exaeta, I've been playing with the ICE40HX8K-B-EVN and I'd recommend it for toying around. But it'll depend on what your final goal is which device/board is best.
<Exaeta> jkiv: I have the 1k right now. I'll have to order the other one(s)
<jkiv> Exaeta, oh, right on
<Exaeta> yosys is not building tho :/
<Exaeta> some problem with "abc"
<Exaeta> and "glucose"
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<jkiv> clang-3.8 the same as clang++-3.8 or isn't one C and one C++?
<jkiv> also, why would one exist on your system and not the other, I wonder
<jkiv> Exaeta, ahh I see what you did
<jkiv> nvm
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<Exaeta> clang is not installed, only "clang-3.8
<Exaeta> what commit do I need to revert to in order to get this to build?
<awygle> Yosys is usually fairly stable. It pins a particular abc commit, so look for the last time that was changed.
<Exaeta> I reverted to the 0.7 tag
<Exaeta> will that work?
<Exaeta> also your makefile doesn't work
<Exaeta> very well
<Exaeta> it looks like cmake
<Exaeta> :/
<jkiv> 0.7 looks like it's nearly 2 years old
<Exaeta> ... erm
<jkiv> err, sorry 1 yea
<jkiv> r
<Exaeta> uhh
<jkiv> Exaeta, which OS?
<Exaeta> what's a commit you have working?
<Exaeta> linux mint
<jkiv> Exaeta, I'll check mine
<Exaeta> 17.3 iirc
<Exaeta> ok it built 0.7... but if that's too old I'll try something newer
<jkiv> Exaeta, I'm on a96c77...
<jkiv> but Ubuntu server 17.10
<Exaeta> should be fine
<Exaeta> it looked like an internal error
<Exaeta> not a system dependency issue
<Exaeta> I guess I need to get started in my hello world verilog stuff now
<Exaeta> any good tutorials while I wait for this to build?
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<jkiv> err, I guess they specify the 8K
<Exaeta> make: *** No rule to make target `/usr/local/share/icebox/chipdb-384.txt', needed by `share/arachne-pnr/chipdb-384.bin'. Stop.
<Exaeta> for arachne-pnr
<Exaeta> do I need that?
<Exaeta> oh nvm ftdi wasn't installed
<Exaeta> aand still doesn't work :/
<Exaeta> oh I have to install icestorm first
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<Exaeta> ok, I don't think blinky works... maybe because it's a 1K instead of 8k? humm
<jkiv> Exaeta, yeah, likely
<jkiv> Exaeta, does your 1k board have leds?
<Exaeta> jkiv: yes, but only 4 that I can see
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<jkiv> Exaeta, yeah, the examples seem to be focused on a particular chip. but, you should be blinking in no time with some minimal edits.
<jkiv> Exaeta, the hardest part is probably figuring out which pins the LEDs are tied to
<Exaeta> jkiv: I did that... D1 to D5... no blinky :(
<jkiv> Exaeta, and updated the makefile? and updated top.v?
<Exaeta> jkiv: wait... what do I need to update?
<Exaeta> I updated pinout.pcf
<Exaeta> I changed "device" from 8k to 1k and it says "supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
<Exaeta> "
<Exaeta> fatal error: unknown package `ct256'
<jkiv> Exaeta, yup, you also have to change "FOOTPRINT" to whichever type of chip is on your board. probably CB132?
<jkiv> Exaeta, start from the left and try each one? Lol
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<jkiv> Exaeta, board documentation should hint toward which ice40 package is on the board. Anyway, best of luck. I'm out for the night
<Exaeta> It's a TQ144 it says so on the chip
<jkiv> Haha perfect
<Exaeta> I need to figure out which pin is the clock though
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<promach> just curious, does yosys do http://vlsi.pro/equivalency-checking-flow-basics/ ?
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<philtor> I see there was some work towards a VHDL frontend for Yosys (https://github.com/forflo/yodl)
<philtor> But it looks like not much has happened there for a couple of years
<philtor> Are there any other VHDL efforts?
<awygle> there have been a few: https://github.com/rqou/yavhdl
<awygle> i dont know that any have really made it very far
<ZipCPU> There is a VHDL front-end for Yosys, but its not open source
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<ZipCPU> There's also a vhdl2verilog package that can turn VHDL to Verilog. I'm told yosys supports it, but I have no experience with it.
<awygle> ZipCPU: is that Verific?
<ZipCPU> Yes.
<ZipCPU> The vhdl2verilog package isn't verific, but yosys does have support for verific's VHDL parser.
<philtor> is this the free VHDL2Verilog translater you're refering to: http://web.eecs.utk.edu/~bouldin/MUGSTUFF/NEWSLETTERS/DATA/1127.html
<philtor> I see that GHDL has an LLVM backend now
<philtor> One would think that might make things easier
<awygle> not necessarily. it depends on how much structure is preserved in the transformation to LLVM. i'm guessing that by the time you get LLVM IR things are already in a pretty simulation-optimized form.
<awygle> if i was going to try to use GHDL i'd probably pay an Ada person to hook in at the AST level, or get a GHDL developer to add AST serialization
<philtor> or become an ADA person :)
<awygle> or whatever their immediately-pre-codegen format is called
<awygle> well, there's always that option :) but my days are full enough
<philtor> So by simulation-optimized you're saying that it's not synthesis-optimal?
<awygle> and i have the impression that ADA is like Lisp, where the people who love it are just happy to have a chance to write it
<awygle> that's my guess, yes
<philtor> Ada has it's strong points
<philtor> ranged types, for example
<philtor> not many languages have that
<awygle> LLVM IR is pretty close to assembly language, meaning it's very CPU-centric and probably doesn't preserve a lot of structure. but again, i haven't actually looked at GHDL
<awygle> (in this context)
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<daveshah> This might also be worth looking at
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<philtor> I asked because I just ordered a BlackIceII board
<philtor> and I tend to prefer VHDL
<philtor> anybody else got a BlackIceII board?
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<philtor> Thought I'd give Yosys a try
<philtor> It's pretty amazing that there's an open source end-to-end synthesis/bitstream creation solution out there now
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<philtor> I recall having discussions about creating such a thing a dozen years or so ago and everyone was skiddish about reverse engineering bitstream formats
<philtor> due to potential lawsuits from the FPGA companies
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<Exaeta> How much does it cost to get an ASIC made?
<Exaeta> Like if I wanted to go from FPGA to real CPU
<Exaeta> (not that I'm anywhere near that)
<awygle> Exaeta: Lots(TM)
<awygle> think 7 figures to start
<awygle> in theory you can get a small batch made on a Multi-Project Wafer for much less
<awygle> but if you want to do, like, production, Lots
<Exaeta> ZipCPU: does the ZipCPU implement instruction pipelining or speculative execution?
<Exaeta> awygle: how much for like, 2-5 ish cpus?
<ZipCPU> Yes, it implements instruction pipelining.
<Exaeta> I don't really care if it's like, 40nm
<ZipCPU> As such, it runs up to 4 instructions ahead of write back. However, memory is not accessed speculatively by design.
<Exaeta> is AM4 well documented?
<Exaeta> awygle: I don't really see any prices listed there
<Exaeta> got an estimation?
<awygle> It Depends (TM)
<awygle> you mentioned 40nm - UMC 40N mixed-mode LP is $72,700 per mm^2, and there's probably a minimum number of mm
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<Exaeta> jesus christ
<Exaeta> lol
<Exaeta> Is it possible to get something cheaper on an older process node?
<Exaeta> like 80nm or something
<awygle> the cheapest one on this list is a 700nm process at $300/mm^2 (again, watch out for minimums)
<ZipCPU> Does that include the masks?
<awygle> i have absolutely no idea if that process would be sufficient for what you want to do. so like i said, depends.
<awygle> ZipCPU: i believe so, but not the packaging. i think the mask is amortized because it's multi-project
<Exaeta> at 700nm, would the FPGAs be faster?
<philtor> Don't forget upfront NRE
<awygle> right, you have to actually engineer it on the process, and if you don't use Magic the tools are $$$$
<awygle> and this, right here, is the limit of what i know about making ASICs. so i will now bow out of the conversation :)
<Exaeta> What I've discovered is that if someone found a way to mass produce cheap masks they could get very very rich .-.
<philtor> Exaeta: are you creating a new CPU?
<ZipCPU> I think the last number I heard for tools was that you could rent them for $4M/yr ... not sure how close that matches actual reality.
<Exaeta> philtor: I would like to. I think I'll stick to FPGA cpu for now
<Exaeta> I don't have millions of dollars .-.
<philtor> Exaeta: yes, probably a good idea unless you can raise a few $Million
<ZipCPU> Exaeta: If you want to build a new CPU, the basic path to success is to first build and prove it on an FPGA.
<ZipCPU> There's a lot of CPU work taking place on FPGA's already today.
<awygle> if you're interested
<Exaeta> ZipCPU: yep. I have some ideas for a CPU right now
<philtor> Exaeta: Some Universities have fascilities to make some chips - they're gonna be a very old process
<philtor> Exaeta: but you might partner with someone in such a place to get a chip made
<Exaeta> ZipCPU: do you know if it's better to make a triple-adder unit or chain two full adders to add three numbers together?
<Exaeta> not that I have yosys working yet
<philtor> Exaeta: I worked at a very small startup that was prototyping in an FPGA. The CEO spent most of his time trying to raise funding for us to spin an ASIC... he never did.
<Exaeta> yeah I think that it'd be easier to funnel money from something else towards making an ASIC .-.
<Exaeta> I'd like to one day create like a GPU with open source drivers that can compete with Nvidia and whatnot.
<philtor> there are some open source GPU projects out there
<Exaeta> I need to get a handle on development first
<Exaeta> I'll work on learning verilog first and then worry about projects.
<Exaeta> My first goal is to make a CPU on fpga
<Exaeta> Does anyone know how to find the hardward clock on the TQ144?
<awygle> Exaeta: can i ask why a CPU is your goal?
<awygle> (just curious)
<philtor> also, if you're just trying to get a CPU running in an FPGA for educational purposes, why not RISC-V?'
<Exaeta> If I can learn to make a CPU it open up options if the process becomes cheaper or somesuch. GPUs and CPUs are very similar in concept.
<philtor> What about a specialized Deep Learning chip? All the rage these days.
<Exaeta> That's very outside my area of expertise.
<Exaeta> And outside my area of talent
<cr1901_modern> Machine learning requires floating point IME. A floating point core is not something you do for a hobby.
<Exaeta> I made a full adder in my computer architecture class without writing a schematic, just plugging wires together, and it worked.
<philtor> Lots of vector adds & multiplies
<Exaeta> My cpu doesn't need to have floating point support
<philtor> cr1901_modern: You can get very good results with fixed point
<philtor> I've worked on a couple of projects where we did FP
<philtor> with good results
<philtor> turns out DL doesn't need high precision
<Exaeta> anyway
<cr1901_modern> But both are a PITA (fixed point much less so)
<cr1901_modern> I'm wary of fixed point b/c once your invariants are violated that your intermediate calculations don't exceed a certain magnitude, you have to redesign.
<philtor> In fact, the newer NVDA GPUs introduced a 16 bit floating point because 32bit was overkill
<Exaeta> anyone know what the hardware clock pin on HX1K TQ144 is ?
<philtor> cr1901_modern: lots of modelling up front
<Exaeta> also the yosys build thingy doesn't seem to know the pin names
<philtor> cr1901_modern: lots of simulating (in your software model) how big your numbers get
<philtor> (where I say we used FP, I mean we used fixed point)
<cr1901_modern> It may be 16-bit, but it's still floating point, nasty edge cases and all. A floating point core is not something you do for a hobby. <-- hyperbole of course, if you want to do it for fun, go for it! Just be aware it's work
<philtor> cr1901_modern: sure, my point being that lower precision is quite acceptable
<philtor> lower precision in fixed point too
<Exaeta> this is quite a problem. I can't even build blinky :/
<philtor> I did an SVM project years ago where I only needed 5 bits of precision
<philtor> Used a lookup table for the gaussian kernel - only needed 64 entries to get as good of results as the C golden program.
<philtor> ended up with a really small FPGA implementation
<philtor> but that was all determined by software modeling up front
<cr1901_modern> Do you still have the project?
<philtor> I'd really have to dig around
<philtor> I'm sure it's somewhere, but this was in like 2004
<philtor> a move and a dead laptop in the meantime
<cr1901_modern> Ack, just wondering
<philtor> University project
<cr1901_modern> Mainly curious about the core's inputs and outputs
<ZipCPU> Exaeta: First step to any project: get the schematics.
<Exaeta> ZipCPU: this is very technical
<Exaeta> supposedly this
<Exaeta> but I search "clock" and nothing shows up :/
<Exaeta> or no it does
<Exaeta> wrong doc
<Exaeta> oh I found it
<Exaeta> But here's an issue I'm getting
<Exaeta> yosys doesn't know any of the pin names
<Exaeta> pinmap.pcf:7: fatal error: unknown pin `X1' on package `tq144'
<Exaeta> oh wait this is the wrong part
<ZipCPU> :)
<ZipCPU> Welcome to working with FPGA's
<ZipCPU> Now it's time for you to discover FPGA Hell ....
<Exaeta> There's no mention of the clock pin in the documentation...
<Exaeta> none
<ZipCPU> Find the schematic, not the user's manual. You'll need the schematic anyway.
<cr1901_modern> I'm afk, but the schematic should be in the user's manual
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<Exaeta> WOOOO
<Exaeta> It works
<Exaeta> pin 21
<Exaeta> 22
<Exaeta> something
<Exaeta> yeah 21
<Exaeta> not very well documented
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<Exaeta> ZipCPU: do you know how to adjust the clock rate or find out what it is?
<ZipCPU> You'll find a nice example of blinky on an ice40 here: https://github.com/ZipCPU/icozip/blob/master/rtl/basic/clktest.v
<ZipCPU> Actually, clktest was what I used for figuring out the clock rate on my icoBoard --- also an iCE40 based board
<Exaeta> Discera 12Mhz MEMS oscillator <- so my board is doing 12MHz... not very fast huh
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<ZipCPU> That plus a PLL gets you any speed you need.
<ZipCPU> icepll will help you choose you PLL settings.
<Exaeta> ZipCPU: is there a way to read input/output over usb?
<Exaeta> like how would I transfer data from pc to ice and vise versa?
<ZipCPU> Most boards have a USB<->UART chip on them made by FTDI.
<ZipCPU> If you have this sort of solution on your board, all you need to do is run a serial port on your board, and read it with your terminal program on your PC.
<Exaeta> For right now, I'd like to get it set up where I can transfer e.g. 4 32-bit integers to the board, and then get a result back, so I can practice verilog
<ZipCPU> UART testing programs: https://github.com/ZipCPU/wbuart32
<ZipCPU> If you want to transfer 32-bits, then look at the discussions of the debugging bus on zipcpu.com
<ZipCPU> Or, look at the repo: https://github.com/ZipCPU/dbgbus
<Exaeta> It was pretty hard for me to get blinky working... I don't think I'll be able to convert that to work on this chip... lol
<Exaeta> maybe I should just wait until I have the same device
<awygle> ZipCPU: have you ever added (e.g.) LZ4 to your debug bus for increased bandwidth?
<ZipCPU> You got it working on your first day? Not bad. Things can get much worse when working with FPGA's. :)
<ZipCPU> No, never LZ4.
<ZipCPU> Although I have added a basic compression.
<ZipCPU> The trick is, any new piece of software that connects to the port needs to be able to start the compression system from scratch, and ...
<ZipCPU> the FPGA doesn't necessarily know when that takes place.
<awygle> i see what you mean
<ZipCPU> The biggest problem with the dbgbus I presented on zipcpu.com is it only uses 4-bits per character. On my favorite one, I'm still only using 6-bits per character. I'd like to move up to seven, just haven't had the opportunity.
<ZipCPU> ... or <gasp> even 8-bits per character!
<awygle> i have an old project that used SLIP (Serial Line Internet Protocol)
<awygle> i am tempted to do that for my upcoming debugging bus
<ZipCPU> That's a completely different protocol though, with different requirements.
<ZipCPU> On the other hand, you might find that, if you can use SLIP for a debugging bus, transitioning to using an ethernet port for debugging becomes even easier.
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<awygle> that was my thought, yes
<awygle> on some level it's all a socket, same tools in call cases
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<Exaeta> ZipCPU: does your CPU have like, MMU type thing?
<Exaeta> where you can have supervisor/os mode and normal mode?
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