<promach__>
ZipCPU: I feel a bit weird that yosys synthesizer cannot recognize the loop as hardware
<promach__>
even if yosys could not recognized as hardware, it should not throw out that error since that loop is only verification testbench code
pie___ has quit [Ping timeout: 240 seconds]
digshadow has quit [Ping timeout: 268 seconds]
digshadow has joined #yosys
<ZipCPU>
promach__: It would do just fine ... if the number of times through the loop was constant.
<ZipCPU>
Think of this as instantiating a circuit, in hardware, ... how many circuits would you build? If you can't tell the number, then you don't yet know how to build it.
<awygle>
promach__: Yosys explicitly deals with synthesizable verilog. I'm not sure to what extent that's been relaxed with the addition of the formal verification features.
promach__ has quit [Ping timeout: 265 seconds]
AlexDani` has joined #yosys
AlexDaniel has quit [Ping timeout: 240 seconds]
AlexDani` has quit [Ping timeout: 256 seconds]
xrexeon has quit [Read error: Connection reset by peer]
promach__ has joined #yosys
dys has joined #yosys
_whitelogger has joined #yosys
_whitelogger has joined #yosys
promach__ has quit [Ping timeout: 260 seconds]
eduardo__ has joined #yosys
eduardo_ has quit [Ping timeout: 260 seconds]
m_t has joined #yosys
gnufan has quit [Ping timeout: 240 seconds]
gnufan has joined #yosys
proteusguy has quit [Remote host closed the connection]
xrexeon has joined #yosys
m_t_ has joined #yosys
pie___ has joined #yosys
m_t has quit [Remote host closed the connection]
awygle has quit [Quit: No Ping reply in 180 seconds.]
awygle has joined #yosys
gnufan has quit [Ping timeout: 256 seconds]
mwk_ has joined #yosys
danieljabailey_ has joined #yosys
promach__ has joined #yosys
gnufan has joined #yosys
indy has quit [*.net *.split]
danieljabailey has quit [*.net *.split]
mwk has quit [*.net *.split]
qu1j0t3 has quit [*.net *.split]
pie___ has quit [Ping timeout: 256 seconds]
indy has joined #yosys
qu1j0t3 has joined #yosys
gnufan has quit [Ping timeout: 255 seconds]
xrexeon has quit [Read error: Connection reset by peer]
<daveshah>
promach__: still looks like it's not looping for a constant number of times
<promach__>
daveshah: it is
<promach__>
check the case() above
dys has quit [Ping timeout: 276 seconds]
<daveshah>
promach__: still looks like Tx_shift_reg_index isn't fixed?
<promach__>
daveshah: huh ? what do you mean ?
dys has joined #yosys
<promach__>
for each cnt, I need to run the for loop
<promach__>
daveshah, do you get it ?
<daveshah>
promach__: yes, but I don't think it'll work the way you have written it. IIRC the loop bounds have to be a synthesis time constant
<promach__>
huh ? how would I go around this ?
<daveshah>
promach__: another `if` statement inside the for loop (i.e. loop from 8 to 0, but only consider the content if index <= Tx_shift_reg_index)
<daveshah>
promach__: but this may generate quite a bit of logic and be slow. A totally different approach may be best, but I can't give you that off the top of my head. Try that solution first anyway
<promach__>
a bit of logic and slow ?? <-- this is only formal verification
<daveshah>
promach__: yes. too much complexity and formal can slow down, in my experience. mostly depends on how big the unconstrained state space is I think
<promach__>
daveshah: I do not understand how putting if statement inside that for loop will help. Care to explain a bit more ?
<daveshah>
promach__: it's just to get the for loop to run a constant number of times
<daveshah>
promach__: so that Yosys can process it