clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach__> ZipCPU: I feel a bit weird that yosys synthesizer cannot recognize the loop as hardware
<promach__> even if yosys could not recognized as hardware, it should not throw out that error since that loop is only verification testbench code
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<ZipCPU> promach__: It would do just fine ... if the number of times through the loop was constant.
<ZipCPU> Think of this as instantiating a circuit, in hardware, ... how many circuits would you build? If you can't tell the number, then you don't yet know how to build it.
<awygle> promach__: Yosys explicitly deals with synthesizable verilog. I'm not sure to what extent that's been relaxed with the addition of the formal verification features.
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<promach__> ZipCPU, awygle: https://gist.github.com/anonymous/e711c6b382d22852e1c0e3a8c3211f08#file-test_uart-v-L188 also does not solve the loop problem. What do you suggest ?
<daveshah> promach__: still looks like it's not looping for a constant number of times
<promach__> daveshah: it is
<promach__> check the case() above
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<daveshah> promach__: still looks like Tx_shift_reg_index isn't fixed?
<promach__> daveshah: huh ? what do you mean ?
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<promach__> for each cnt, I need to run the for loop
<promach__> daveshah, do you get it ?
<daveshah> promach__: yes, but I don't think it'll work the way you have written it. IIRC the loop bounds have to be a synthesis time constant
<promach__> huh ? how would I go around this ?
<daveshah> promach__: another `if` statement inside the for loop (i.e. loop from 8 to 0, but only consider the content if index <= Tx_shift_reg_index)
<daveshah> promach__: but this may generate quite a bit of logic and be slow. A totally different approach may be best, but I can't give you that off the top of my head. Try that solution first anyway
<promach__> a bit of logic and slow ?? <-- this is only formal verification
<daveshah> promach__: yes. too much complexity and formal can slow down, in my experience. mostly depends on how big the unconstrained state space is I think
<promach__> daveshah: I do not understand how putting if statement inside that for loop will help. Care to explain a bit more ?
<daveshah> promach__: it's just to get the for loop to run a constant number of times
<daveshah> promach__: so that Yosys can process it
<promach__> huh ? how ?
<promach__> daveshah: "if(index <= Tx_shift_reg_index)" ?
<daveshah> promach__: yes exactly
<promach__> why ?
<promach__> daveshah: your suggestion does not solve the problem
<promach__> :|
<daveshah> promach__: odd
<daveshah> promach__: what is your code now?
<promach__> is the if statement inside or outside the for loop ?
<daveshah> promach__: inside
<daveshah> promach__: and the loop bounds are fixed
<daveshah> promach__: your loop bounds are still not a synthesis time constant
<promach__> what ?
<daveshah> promach__: you also need to write `for(index=8; index>0; index=index-1) begin)`
<daveshah> *ignore the last `)`
<promach__> daveshah: what about the case() above ?
<daveshah> promach__: that can stay, as you need Tx_shift_reg_index for the `if` statement
<promach__> daveshah: however if I write "for(index=8; index>0; index=index-1)" , I need to have write this for() for every cnt ?
<daveshah> promach__: no
<daveshah> promach__: the if statement inside takes care of that?
<promach__> let me try
<promach__> daveshah: thanks, that helps
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<dmin7> evening
<dmin7> is there any documentation on the MachX02 firmware?
<dmin7> (for the icoboard)
<ZipCPU|Laptop> dmin7: Howdy!
<ZipCPU|Laptop> As I recall, I looked into it a while ago.
* dmin7 trying to modify icoprog to work with the icezero, but i don't really understand how the flashing works for the icoboard x)
<ZipCPU|Laptop> Flashing is the easy part to understand, the machxo2 ... well, I never found the code for that.
<ZipCPU|Laptop> I managed to reverse engineer what I needed from the schematic, and from the icoprog tool.
<ZipCPU|Laptop> In the end ... I managed to make a nice comms system between the RPi and the board, but I did that using the parallel port.
<dmin7> ok, i guess i'll try to understand whats going on in the icoprog.cc code more
<ZipCPU|Laptop> I found a tool for loading the MachXO2 ... just not what the original source code was.
<ZipCPU|Laptop> Ahh ... that's just a pass through to the config SPI port on the device.
<ZipCPU|Laptop> Be aware ... about 50% of the logic in my copy of icoprog.cc (from the repo) is unused and superfluous code
<ZipCPU|Laptop> Look for the access using wiringPi
<ZipCPU|Laptop> Consider USBMODE to be undefined ... that should simplify your examination.
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<dmin7> huh, it works! :)
<dmin7> i used iczprog for the icosoc.bin, and then just adjusted the data/raspi_interface pins in icoprog and used that to 'flash' the appimage
<dmin7> icezprog*
<ZipCPU|Laptop> Nice
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