<ZipCPU>
Yeah ... that won't work because the synthesizer can't tell how many times to run the loop.
<ZipCPU>
The number of counts through the loop is dependent upon a changing value, stop_bit_location_minus_one
<promach__>
ZipCPU: check line 78
<ZipCPU>
You realize ... you are programming hardware, not software here, right?
<ZipCPU>
yosys is going to use your loop to create a fixed number of hardware circuits. If it can't figure out how many circuits to generate, it will give up with the error it just gave you.
<promach__>
ZipCPU: ok
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<promach__>
ZipCPU: it means either I need to physically unroll the loop for the synthesizer OR I have to wrote case() for each count ?
<promach__>
induction is just giving me this loop problem to solve during holiday ...
<ZipCPU>
Yes.
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<hanetzer>
heyo. figured you guys would know, is there any open tooling for altera max cpld's available? Its not really that important, but a BIOS POST card I just got uses one so it piqued my interest a bit.
<awygle>
hanetzer: not to my knowledge
<awygle>
hanetzer: well, Yosys may support synthesis for them, but certainly there is no routing or bitstream generation or anything
<hanetzer>
awygle: k. just a bit of idle curiosity as I said.
<awygle>
looks like synthesis support for max10 exists at least
<hanetzer>
I'm probably gonna grab an icestick for my needs, doing a bit of EC/LPC sniffing for a laptop
<hanetzer>
coreboot port in progress :)
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