clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<thoughtpolice> daveshah: sorry for no reply -- I'd be interested in your experiences with it! I kind of wanted to ask for the library copy Verific to test its SystemVerilog support. When I was looking around for a way of testing Clash's SystemVerilog backend, it was hard because there are no real free simulators, and I had the crazy idea of trying to use Yosys/Verific to translate to Verilog and run our Icarus simulations that way, haha
<thoughtpolice> daveshah: I am also interested in the formal verification experiences too :)
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<daveshah> thoughtpolice: I've mostly been using it for VHDL, for which it's worked well - my formal work has been using a SystemVerilog testbench to verify VHDL. I do think your idea might work, but I can't help you with the copy of verific at this stage unfortunately (try asking Clifford perhaps?)
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<thoughtpolice> Well I don't want to be a bother; I didn't ask because I figured they wouldn't give it. :) A lot of software places can be sympathetic to open source projects in terms of resources. sometimes, but hardware not so much.
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