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ZipCPU>
So ... I spent today trying to understand system verilog's concurrent assertion language.
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ZipCPU>
Now I think Clifford gave us a gift by
*not* including it in yosys.
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awygle>
ZipCPU: oh? do tell
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tpb>
Title: gist:6ae69cc05e13e412d0389d11685f7a70 · GitHub (at gist.github.com)
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ZipCPU>
awygle: Those are some wishbone bus properties in the concurrent assertion subset of System Verilog.
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ZipCPU>
While I like the language for its expressive ability, it's ... not nearly as easy to read and comprehend.
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ZipCPU>
cr1901_modern: Yeah, I was referencing that tutorial a
*lot* yesterday.
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