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<bthom>
Hi, Is it possible to get from yosys the maximum level of logic between every dff? (In it's internal cell representation) I was considering computing it myself based on the graph output, but I thought this functionality may already be implemented in a part that I did not find in the doc.
<ZipCPU>
You mean ... like the longest path length?
<ZipCPU>
Are you asking regarding an ice40, or some other chip?
<bthom>
Yes the longest path length, but not for ice40, for the "Internal cell" that are described in the documentation of yosys. (So before using the final libraries, if I understand a bit the flow of yosys)
<ZipCPU>
Yeah, not sure I know that answer.
<ZipCPU>
bthom: Would "ltp" (longest-topological path) work for your purpose?
<ZipCPU>
-noff will exclude FF cell types
<ZipCPU>
... and you'll probably want to flatten your design first.
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<bthom>
That sounds great! Thanks for the tip, I will try it out right now
<bthom>
*hint
<bthom>
That works great, thank yoU!
<ZipCPU>
I love taking credit for what other people do ... :D
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