clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<FL4SHK> There is a VHDL frontend for yosys in development, isn't there?
<FL4SHK> wh
<FL4SHK> I just... saw something in Yosys
<FL4SHK> SystemVerilog interfaces are supported?!
<FL4SHK> packages are supported?
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<mithro> ZipCPU: you should join #symbiflow - Your ears should be burning :-)
<bubble_buster> any other good related channels? I'm already in ##openfpga as well
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<ZipCPU> ##verilog? ##dsp #cpudev
<ZipCPU> There's an #openrisc channel, and a #risc channel too, but they've been somewhat quiet
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<FL4SHK> Well, I tried synthesizing SystemVerilog interfaces with yosys.
<FL4SHK> ...It seemed sketchy?
<FL4SHK> Mostly because I tried ports, I guess
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