clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> For https://gist.github.com/promach/cf3ae626a85badad6cd822d3107c86b7#file-spidergon_router-v-L343 , why am I having this error "[spidergon_proof] base: spidergon_router.v:343: Warning: Range [1:-1] select out of bounds on signal `\data_input': Setting 1 LSB bits to undef." ?
<tpb> Title: Spidergon Networks On Chip · GitHub (at gist.github.com)
<promach> If I change (FLIT_DATA_WIDTH-1) to 7 , I have different error
<promach> it seems like the verilog code parser treats (FLIT_DATA_WIDTH-1) and 7 differently. Note that FLIT_DATA_WIDTH has a value of 8
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<promach> ZipCPU: have you experienced similar issue previously ?
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<ZipCPU> promach: Yes, I have had similar issues, but the were all traced in the end to issues within my own code
<ZipCPU> In your case, lines 7-9 are missing the keyword "parameter" as are 11-13
<promach> ZipCPU: no
<promach> I have added parameter as you advised, but same error
<promach> I think I know why now
<promach> I have one other bug
<promach> I just got past this particular error
<ZipCPU> I usually catch errors like these using Verilator--even if I don't synthesize with Verilator
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<promach> now, I really like verilator linting feature
<promach> ZipCPU
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<ZipCPU> Why, did you find your bug?
<promach> ZipCPU: verilator linting provides some other insights into my coding
<ZipCPU> ;)
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<FL4SHK> Verilator is really high quality software
<FL4SHK> I've honestly considered switching to it for when I just need a simulator.
<FL4SHK> It's le fast
<FL4SHK> I'm surprised that GHDL is a GCC front end....
<FL4SHK> Holy crap is that cool
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