clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<corecode> m
<corecode> oups
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<FL4SHK> It appears that yosys doesn't know about SystemVerilog interfaces used on ports. Oh well.
<corecode> yea i had to go back to plain verilog
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<FL4SHK> corecode: Give me a while (at least a few more months). I'm developing a compiler thing for a SystemVerilog-like HDL that will just spit out Verilog.
<FL4SHK> Actually, I think it'll spit out yosys-compatible SystemVerilog.
<FL4SHK> Perhaps not
<FL4SHK> I'll have it spit out Verilog.
<FL4SHK> Oh, and I mean it'll be similar to synthesizable SystemVerilog.
<FL4SHK> I don't know how I'd convert the dynamic stuff to Verilog (strings, handle-based classes, dynamic arrays, etc.)
<FL4SHK> ... and I've chosen to unify code block syntax: everything is {}
<FL4SHK> Concatenation looks like a function :P
<FL4SHK> concat(a, b)
<FL4SHK> I also cut out a lot, I guess.
<FL4SHK> But not much of any interest to synthesizing into FPGA code
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<litghost> daveshah: I haven't seen any activity on https://github.com/YosysHQ/yosys/pull/928 , is it in an acceptable form?
<tpb> Title: Add additional cells sim models for core 7-series primitives. by litghost · Pull Request #928 · YosysHQ/yosys · GitHub (at github.com)