clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<FL4SHK> oooh
<FL4SHK> maybe I'm not running the right commands
<FL4SHK> "failed to detect width for identifier"
<FL4SHK> ooooh
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<FL4SHK> it appears that I've found a bug
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<tpb> Title: [VeriLog] module top(BTN1, BTN2, BTN3, LED1, LED2); input BTN1, BTN2, BTN3; output L - Pastebin.com (at pastebin.com)
<tnt> At line 6, is that valid in verilog ?!?
<corecode> the initializer
<corecode> ?
<tnt> LED are the outputs
<corecode> oh
<corecode> then i don't understand what this is supposed to do
<tnt> well my guess is the author just assumed it woudl 'connect' Sum[0] with LED1 'bidirectionally'.
<tnt> like a physical wire ...
<corecode> i see
<tnt> but afaik ... it's wrong.
<corecode> yes, that seems wrong
<tnt> and yet yosys seems to accept it.
<corecode> it looks like an initializer
<daveshah> Yosys and LSE both seem to treat the = as bidirectional, Synplify and Verilator seem to treat it as unidirectional
<corecode> oh interesting
<corecode> i mean it doesn't make much sense to use an output as RHS?
<tnt> I usually try to avoid it ...
<tnt> I know in VHDL it's just forbidden.
<corecode> the standard calls this net_decl_assignment
<corecode> and it's in the 6.1 continuous assignment section
<corecode> so that means there are two continuous assignments
<tnt> yeah and the way I read it, it's clearly unidirectional. Value is _driven_ on the LHS whenever the RHS _changes_.
<corecode> yes
<corecode> can an output port be readable?
<tnt> I'm trying to find that in the spec right now.
<corecode> there are examples that imply that you can use output ports as RHS
<corecode> 12.1.2
<corecode> i think it matters only for the module using the submodule
<tnt> yup, afaict they are just normal wires so you can 'read' their values.
<corecode> yea
<corecode> so in this case, the problem is that there are two conflicting continuous assignments
<corecode> and something bidirectional going on as well?
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<FL4SHK> Did anyone happen to see what I mentioned last?
<FL4SHK> I think I found a bug in yosys's SystemVerilog support.
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<FL4SHK> well, I've made a fork. I'll see if I can fix it myself.
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